Arbeitskreis MOS-Modelle und Parameterextraktion MOS Modeling and Parameter Extraction Working Group MOS-AK/ESSDERC/ESSCIRC Workshop

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Agenda: Sept. 18 2009 in Athens
Morning Session 9:00-11:30 Oral presentations 10:00-10:30 (coffee break)	Poster Session 11:30-12:00 Posters 12:00-13:00 (lunch)	Afternoon Session 13:00-16:00 Oral presentations 14:30-15:00 (coffee break)

"Frontiers of Compact Modeling" Workshop Program

Display Format: Citation Citation & Abstract
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Venue	DIVANI CARAVEL HOTEL, 2 Meg. Alexandrou Aven. 161 21, Athens, Greece For driving directions please visit: www.ametro.gr and www.oasa.gr
11:30-12:00	Poster Session
P_a	40nm Model Library Insight James Ashforth-Pook Accelicon Europe Abstract:  TBD
P_b	Advanced Open IDM Model Eugen Pfumfel Toshiba Europe Abstract:  TBD
P_c	Electronic Semiconductor Characterization Tool (ESC) Mostafa Emam, César Roda Neve, Danielle Vanhoenacker-Janvier and Jean-Pierre Raskin Microwave Laboratory (EMIC), Université catholique de Louvain, 1348 Louvain-la-Neuve (Belgium) Abstract:  The characterization of active devices, either in dc or in RF, is rather important, not only for the correct understanding of the device behavior, but it also helps to enhance the fabrication steps and procedures. The diversity of active devices, such as MOSFET, BJT, HBT, etc., has led to the development of a large number of extraction methods in the literature, both in dc and RF. The validity of these extraction methods is sometimes limited to a certain device type, to a restricted frequency range, to some specific bias points or to a combination of these conditions. As a result, a need is raised to create an environment which includes all these extraction methods in a way to be able to compare them, criticize them and choose the more appropriate method for the device under the required conditions. This tool, Electronic Semiconductor Characterization tool (ESC), is developed in Matlab. It also helps to develop new extraction methods which are more adequate and more reliable for the considered device and regime of operation. The tool is based on generic routines that can be extended to include new devices while keeping it simple and away from complicated and time-consuming optimization techniques.
P_d	Simulation study of digital circuits based on nanometric Surrounding Gate Transistors: the role of quantum and velocity overshoot effects A.M. Roldán, J.B. Roldán, F. Gámiz Departamento de Electrónica y Tecnología de Computadores. Universidad de Granada (Spain) Abstract:  CMOS circuits based on Surrounding Gate Transistors (SGTs) have been studied in depth. To do so, a new compact model has been developed and implemented in Verilog-A. Quantum, velocity overshoot, short channel and saturation velocity effects have been taken into account. The quantization of the inversion layer has been characterized by means of an inversion charge centroid model obtained by comparison with the results of a two dimensional self-consistent Poisson and Schrödinger simulator, and a new capacitance model. The influence of quantum and velocity overshoot effects, which are known to be severe in current digital microelectronic technologies, is studied in several CMOS digital circuits based on nanometric SGTs. In particular, a seven stage CMOS oscillator ring has been simulated to characterize the oscillation frequency.
P_e	A new compact model for short-channel, symmetric double gate MOSFET Anna Sawicka, Lidia Lukasiak and Andrzej Jakubowski IMIO PW (Poland) Abstract:  A new model of drain current for a symmetrical, undoped DG MOSFET is presented. The model is based on the long-channel core compact model of Sallese et al. Several solutions for short-channel effects (dependence of threshold voltage on channel length, velocity saturation, channel-length modulation, drain induced barrier lowering and drain-induced charge enhancement) were added to the core model in order to extend its validity for short-channel devices. The accuracy of the model was verified by means of a comparison with ATLAS simulations. Comparisons of I-V and C-V characteristics with the results of 2D numerical simulations for channel lengths down to 20nm over a wide range of bias conditions show very good overall behavior. The model is physics-based, simple and efficient, hence applicable for circuit design. It was implemented in the hardware description language Verilog-A and applied in several simulations of simple analog circuits in order to demonstrate its usefulness.
P_f	Modeling of the subthreshold characteristics of Triple-Gate Transistors: impact of the channel dimensions and back-gate bias Romain Ritzenthaler, Francois Lime and Benjamin Iniguez Rovira i Virgili University (Spain) Abstract:  In this work, the subthreshold characteristics of long channel Triple-gate transistors are studied. Solving the 2D Poisson’s equation in the subthreshold regime, models for the threshold voltage, the subthreshold slope and the subthreshold current can be derived. The complete solution is a Fourier series development. In order to make the modeling tractable, the solution can be cut at the first order to get an average accuracy, or adjusted with geometrical fit parameters in order to increase the precision. It is shown that the threshold voltage of a Triple gate transistor is highly dependant of the width and height of the channel, and of the back-gate bias. Depending on the bias, the back-gate will be driven in different regimes modifying the threshold voltage (real threshold voltage(s), or ‘measured’ one(s)). Using narrow enough channels and/or correct biasing of the back-gate/engineering of the flat band voltage of the back-gate, all these dependences can be very significantly reduced. A modeling criterion giving the dimensions where the effect of the back-gate can be neglected has equally been extracted. The models have been validated using a commercial 3D numerical device simulator and compared to experimental devices.
P_g	A Unified Analytical, Physical and Scalable Lumped Model of RF CMOS Spiral Inductors Siamak Salimy*,***, Antoine Goullet**, Ahmed Rhallabi**, Serge Toutain*, Fatiha Challali**,***, Jean Claude Saubat*** *IREENA (France), **IMN (France), ***MHS Electronics (France) Abstract:  Scalable and physical compact model of integrated passive device in CMOS technology are today required by designers to easily predict the frequency response of the component and estimate the parasite elements influence. A scalable and analytic approach is proposed here to model spiral inductors and MIM capacitors. By considering layout and technology parameters, under quasi-static approximation, the model elements are all expressed analytically and based on physical assumptions. The proposed approach provides simple physical and electrical interpretation for passive component design. The models are suitable to be easily implemented in design kits by foundry and provide sufficient accuracy to be used by CMOS Radio Frequency Integrated Circuits designers.
P_h	Closed-form Current Equation for Short-Channel Triple-Gate FETs Alexander Kloes* and Michaela Weidemann*/** and Mike Schwarz*/** *University of Applied Sciences Giessen-Friedberg (Germany), **Universitat Rovira i Virgili (Spain) Abstract:  Current flow in short-channel triple-gate FETs is strongly influenced by three-dimensional effects. In subthreshold operation the current is located in the device center, whereas above threshold the inversion channel moves to the silicon-to-oxide interface. This movement of the most leaky path can result in an abnormal behavior in the transconductance. In this poster a way is presented how channel charge below threshold, derived from a three-dimensional solution of Poisson’s equation, and channel charge above threshold, calculated from bulk MOS equations, can be combined to define a single closed-form current equation for triple-gate FETs. The current model correctly predicts geometry effects on the transconductance. It is in good agreement with numerical results from TCAD down to a channel length of 30nm.
P_i	Optimization of a RF CMOS technology for high Q inductors Volker Mühlhaus*, Gerhard Metzger-Brueckl** and Christophe Holuigue*** Muehlhaus*, LFoundry**, Analog Alchemy***  (Germany) Abstract:  In this paper, an electromagnetic (EM) analysis based inductor design flow is applied to optimize the performance of on-chip spiral inductors in a 150nm RF CMOS process. The technology is aimed at, and optimized for, high frequency designs. The possible improvement in Q factor from a thick 6µm Al layer and a possible substrate back etching option are analysed. These enable the design of inductors with high quality factor at radio frequencies, by providing a large conductor cross section while at the same time minimizing the substrate induced losses. The effect of these technology parameters on the inductor Q factor in the frequency range 2.4 and 5.8GHz is discussed in detail and compared to results obtained with standard technologies. To verify the analysis, simulation results are compared to measurements.
P_j	Characterization and Modeling of Single Event Transients in LDMOS-SOI FETs Joaquin Alvarado, Valeria Kilchystka and Denis Flandre Microelectronics Laboratory, Université catholique de Louvain (Belgium) Abstract:  In this paper, we investigate single event transient (SET) phenomena in LDMOS-SOI devices. Three-dimensional simulations and a modified compact model are coupled in order to reproduce the current pulse generated by an ion strike, at different locations, through the LDMOS-SOI device, compared to a Partially Depleted SOI MOSFET. A comparable charge collection in the PD SOI and the LDMOS can be observed, because while PD SOI possessed higher electric field and hence current peaks, the LDMOS exhibits longer transient durations, giving as a result about the same collected charge. Nevertheless, PD SOI shows slightly higher collected charge and hence seems to be slightly more sensitive to the SET than LDMOS. Results obtained by the compact model agree qualitatively with simulation allowing faster predictions of the critical charge without extensive simulations.
P_k	Improving Calibration Accuracy of Wafer-Level Measurement System for Confident Over-Temperature RF Device Characterization Andrej Rumiantsev and Stojan Kanev SUSS MicroTec Test Systems GmbH (Germany) Abstract:  This poster will present the results of accuracy verification of wafer-level calibration at high temperatures based on coplanar calibration standards. The electrical characteristics of commercially available coplanar lines as well as lumped calibration standards were extracted and compared at different temperatures. The accuracy of different calibrations schemes was verified at variable temperatures by definition of the worst-case error bounds for the measurement of passive devices and compared to the reference NIST multiline TRL. Finally, recommendations on how to improve measurement accuracy at high temperatures are given.
P_l	Improvements to α-Si RPI-TFT model: now extrinsic and with correct account of the positive differential conductivity after saturation V.O. Turin*, A.V. Sedov*, G.I. Zebrev**, B. Iñiguez***, and M.S. Shur**** *OrelSTU  (Russia), **MEPHI (Russia), ***URV (Spain), ****RPI Troy (USA) Abstract:  We introduce an improved TFT model based on the RPI compact model. The new model accurately describes the output conductance in the entire range of drain and gate bias voltages. We revise the approach based on the channel-length modulation parameter λ0 to account for positive differential conductivity after saturation. The traditional approach suffers from non-monotonic behavior of the differential conductivity with an increasing drain-to-source bias at small bias values. Our new approach provides for the correct monotonic decrease of the differential conductivity. This is done by first introducing a new asymptotic "after saturation" equation for the drain current. This equation was derived from the condition, that asymptote should be tangential to the output characteristic before saturation in Charge-Sheet Model (CSM). Second, we use a Hölder mean with exponent -m of the linear part of the CSM output characteristic before saturation and the new equation for drain current after saturation. Note that instead of using here new asymptotic "after saturation" equation we need to modify one as discussed in our presentation. We have transformed the RPI model into an extrinsic analytical model that accounts for the source and drain series resistances. The suggested improvements could be useful for most FETs compact models used in modern compact circuit simulators.
12:00	End of the Poster Session
Committee	Benjamin Iniguez, URV; Technical Program Chair Matthias Bucher, TUC; ESSCIRC Tutorials and Workshops Chair Charalambos Dimitriadis, Uni Thessaloniki; ESSDERC Tutorials and Workshops Chair Pekka Ojala, Exar; MOS-AK/GSA WG North America Chair Gilson I Wirth; UFRGS; MOS-AK/GSA WG South America Chair Ehrenfried Seebacher, austriamicrosystems AG; MOS-AK/GSA WG Europe Chair Al Kordesch, Silterra Malaysia; MOS-AK/GSA WG Asia/Pacific Chair Chelsea Boone GSA; Senior Research Analyst Darryl Leavitt, GSA; Director of Events Wladek Grabinski, GMC Suisse; MOS-AK/GSA Workshop Manager

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update: Sept.28 2009 (rev. a)

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