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aBook

Transistor Level Modeling for Analog/RF IC Design

Editors: W.Grabinski, B.Nauwelaers, D.Schreurs
Publisher: Mark de Jongh [Mark.deJongh@springer-sbm.com]
ISBN: 1-4020-4555-7; 2006, Approx. 290 p., Hardcover
www.
springer.com
Front_Cover_CN 模 拟/射频集成电路设计的晶体管级建模
著译者:W.Grabinski, B.Nauwelaers, D.Schreurs
标准书号: 978-7-03-018241-8
出版时间: 2007-01-27
www.sciencep.com
Table of contents Chapters Chapters & Paragraphs
Foreword
   Hiroshi Iwai, Tokyo Institute of Technology

Introduction
   Wladek Grabinski/Bart Nauwelaers/Dominique Schreurs

2/3-D Process and Device Simulation
– an effective tool for better understanding of internal behavior of semiconductor structures

   Daniel Donoval1, Andrej Vrbicky1, Ales Chvala1, and Peter Beno2
   1 TU Bratislava, 2 ON Semiconductor Slovakia

PSP: An Advanced Surface-Potential-Based MOSFET Model
   Ronald van Langevelde; Philips Research and Gennady Gildenblat; PSU

EKV3.0: An Advanced Charge Based MOS Transistor Model
   Matthias Bucher1, Antonios Bazigos2, Francois Krummenacher3, Jean-Michel Sallese3, Christian Enz3
   1 TUC, 2 NTUA, 3 EPFL

Modelling Along the Measurement Spectrum
   Dominique Schreurs; Telemic KUL

Empirical FET Models
   Iltcho Angelov, U. Chalmers

Modeling the Nonlinear Behavior of SOI MOSFETs
   Bertrand Parvais; UCL, and Alexandre Siligaris; IEMN

Circuit Level RF Modeling and Design
   Nobuyuki Itoh; Toshiba

On Incorporating Parasitic Quantum Effects in Classical Circuit Simulations
   Frank Felgenhauer, Maik Begoin and Wolfgang Mathis; TU Hannover

Compact Modeling of the MOSFET in VHDL-AMS
   Christophe Lallement, François Pêcheux, Alain Vachoux and Fabien Prégaldiny, InESS/LIP6/EPFL

Compact Modeling in Verilog-A
   Boris Troyanovsky, Patrick O'Halloran and Marek Mierzwinski; Tiburon Design Automation, Inc.

update 21-Aug-05  No.#4615All rights reserved. WG  ©2005-2007