Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
Virtual Spring MOS-AK Workshop
THM Giessen (D), Sept. 29 - Oct. 1, 2020
Calendar
Open Directory
Books
Mission
Committee
MOS-AK: Enabling Compact Modeling R&D Exchange
MOS-AK Techical Program Promoters
 
THM
IEEE EDS
IEEE IEEE_YP_Germany
AdMOS SSE Publication Partner
Publication Partner
Final Program of Virtual MOS-AK/Giessen 2020 Workshop
Important Announcement: Due to very recent COVID-19 regulations at THM, no events gathering of the external attendees are allowed in the next weeks. These rules are pure precautionary measures, which apply until April 30 and should help to minimize the infection risk at the THM campus. MOS-AK Workshop shedulled for March 17-18, 2020 with Symposium on Schottky barrier MOS devices and IEEE EDS Mini Colloquium "Non-conventional devices and technologies" will be organized as a virtual event with new dates:
Dates:
  • Tue 29.09.2020 - MOS-AK
  • Wed 30.09.2020 - MOS-AK & IEEE EDS MQ
  • Thu 01.10.2020 - IEEE EDS MQ & SB MOS Symposium
Venue: Competence Center for Nanotechnology and Photonics
THM Giessen (Virtual Rooms)

FreeOnline Registration: https://meetings.vtools.ieee.org/m/205571
TUE: 29.09.2020 (Virtual Room)
 9:35-09:50 Welcome and Opening MOS-AK Workshop
A.Kloes, THM and W.Grabinski, MOS-AK
 Session Chair: A.Kloes, THM
 Canceled M1: THz Schottky detectors based on GaAs and InGaAs materials using metallic NWs or evaporated finger contacts
Ahid S. Hajo, Oktay Yilmazoglu, Franko Küppers and Thomas Kusserow,
TU Darmstadt (DE)
 9:50-10:10 M2: Fabrication and Application of Nanocrystalline Diamond Thin Films
and Hybrid Diamond-Silicon Sensor Applications
Abstract
Nanocrystalline and ultrananocrystalline diamond combines the remarkable properties of conventional diamond, such as extreme hardness and wear resistance. Here, we report on the correlation between grain size and relevant physical and chemical properties of phase pure NCD and UNCD layers synthesized by chemical vapour deposition on silicon single crystal wafers with diameters up to six inches. The UNCD films consist of ultra-small (ca. 5 nm) equiaxed grains resulting in ultra-smooth surfaces with surface roughness equivalent to the grain size. The mechanical properties show that due to the large number of grain boundaries with highly disordered atomic structure the Young’s modulus is decreased from about 1010 GPa to 500-700 GPa and fracture strength is increased from 1 GPa to ca. 5 GPa. The electrically conductive UNCD layers exhibit a piezoresistive effect which makes it useful for sensing applications. As a step further, by a combination of photolithographic masking and controlled reactive ion etching processes, complex shaped microparts are designed and fabricated. Some applications will be discussed, such as a prototype silicon-diamond hybrid pressure sensor for harsh environments.
Markus Mohr, Hans-Jörg Fecht Ulm University, Institute of Functional
Nanosystems (DE)
COFFEE BREAK
Session Chair: W.Grabinski, MOS-AK
10:50-11:10 M3: Statistical circuit analysis by NOVA (Noise Based Variability Approach)
Abstract
Organic thin-film transistors (OTFTs) are commonly used as the basic building blocks for low-cost large-area electronic circuit applications such as foldable information displays, plastic circuits, printed bio-sensing configurations and active-matrix organic light-emitting diode (AMOLED) displays. Process variability during OTFT fabrication, introduces variations into the transistor’s main electrical parameters namely threshold voltage, mobility and channel dimensions. Consequently, circuit properties are affected accordingly. Monte Carlo (MC) simulation is commonly used to determine the performance of OTFT based circuits versus parameter variability. MC consists of a sequential number of simulations where for every iteration, a parameter set is randomly varied and the circuit is simulated accordingly. Subsequently, the statistical results are collected and the yield of the circuit is estimated. For reliable approximations, MC analysis requires a large number of iterations resulting into a significantly increased processing time. Here, a MC alternative for fast statistical circuit analyses will be presented. The proposed method is based on circuit noise simulation principles and can be abbreviated as NOVA (Noise Based Variability Approach). NOVA is applied in OTFT based circuits for both process and mismatch statistical analysis study. Overall, NOVA circuit analysis can be used effectively for Gaussian shaped statistical distributions and presents significant time improvement when compared to the conventional MC simulation.
Aristeidis Nikolaou*, Jakob Leise*, Jakob Pruefer*, Ute Zschieschang**,
Hagen Klauk**, Ghader Darbandy*, Alexander Kloes*,
*THM (DE), **Max Planck Institute for Solid State Research Stuttgart (DE)
11:10-11:30 M4: Approaches for analytical (compact) modeling of tunneling current in MOS transistors
Abstract
Today, MOS transistors in new technologies are aggressively scaled. In these devices tunneling currents became more important. Source-to-drain tunneling in ultra-short-channel MOSFETs contributes to their leakage current. Furthermore, new device concepts as e. g. the Tunnel-FET are under investigation, in which tunneling currents are beneficially employed as the dominating type of carrier transport mechanism. Compact modeling must provide numerically efficient solutions to describe tunneling currents in a framework for circuit simulation, preferably while keeping physical insight. In this talk approaches for physics-based and numerically efficient calculation of tunneling currents are reviewed (WKB, Wavelet and NEGF) and their benefits for compact modeling evaluated.
Alexander Kloes, THM Giessen (DE)
LUNCH BREAK
Session Chair: Ghader Darbandy, THM
13:00-13:20 M5: Modeling of GaN HEMTs on Silicon Substrate
Abstract
Gallium Nitride (GaN) technology is on the verge of industrial utilization in the fields of power electronics and high-frequency technology. Due to its advantages like high breakdown voltage, low on resistance and high operating temperature. They have potential to be used in THz frequency region. This creates a new demand for special and new characterization and modelling methods. The reason behind this is the complex crystal structure formed by electronegative Ga and N atom. Modeling all the real device effects is a challenge. This is where the project “GaNScan” funded by the German Federal Ministery of Education and Research comes into the picture. A partial aim of this project is to further develop and improve the industry standard model (Compact Model Council-CMC) ASM-HEMT. There are mainly three project partners involved in this project: IMS Chips Stuttgart, RoodMicrotec GmbH and AdMOS GmbH. Within the scope of this project, various advancements in the simulation model have been identified and published. Enhanced or new equations for important aspects like device temperature scaling, gate length scaling and surface potential-based device performance were developed and implemented in the Verilog-A code of ASM-HEMT. Experimental data from several sources allowed a verification of all mentioned improvements. Success of GaNScan project will further strengthen the base of future developments in the field of GaN device simulation models and hence GaN device circuit designs.
Mahimna Dwivedi*, Sayed Ali Albahrani*, Thomas Gneiting*, Lars Heuken**, Joachim Burghartz**
*AdMOS GmbH (DE), **IMS Chips (DE)
13:20-13:40 M6: Adopting the Industry-standard CMOS Models for Si Vertical Power MOSFETs
Abstract
Currently optimized circuit design suffers from the lack of accurate and robust models for vertical structure power transistors, and designers often encounter problems in terms of platform compatibility and interchangeability of the vendor models. On the other hand, for CMOS logic devices, industry standard compact models, like the BSIM and EKV family, are proven to be accurate and robust. However these standard models cannot be directly applied to the power devices , since the device structure of power MOSFETs (vertical, trench-MOS) is typically very different from standard CMOS type transistors (lateral) for logic processing. This work presents a modeling approach adopting the industry standard model BSIM3.3 and EKV2.6 with specific structural for a Si vertical power MOSFET. The standard models, which are developed for CMOS logic devices, are evaluated and adopted to describe the channel behavior of the power MOSFETs, and their performances are compared. Meanwhile, the extended components including the non-linear drift resistance, body-diode and drain-gate capacitance are defined according to the vertical MOSFET structure which is different from conventional CMOS devices. The temperature-dependent parameters in the original standard model expressions are used to contribute to an improved dynamic thermal model, which describe the thermal behavior of the device more close to the realistic power transistor operation. The parameters of the model are extracted based on the measurement of the characteristics of the device. The static characteristics are measured by a curve tracer. Considering the frequency dependency of the intrinsic capacitances of power MOSFETs, the capacitance characterization is based on a 2-port S- parameter measurement. A suitable parameter extraction procedure is defined to efficiently extract the model parameters. The parameter extraction result shows that the proposed model is able to describe the device characteristics precisely.
Lixi Yan, Ingmar Kallfass, Insitute of Robust Power Semiconductor Systems,
University of Stuttgart (DE)
COFFEE BREAK
Session Chair: Laurie Calvet, Uni. Paris-Saclay
14:10-14:30 M7: Overview of Gnucap, the GNU Circuit AnalysisPackage
Abstract
This talk will give an overview of Gnucap, the GNU Circuit Analysis Package, with emphasis on current work, including plugins and "modelgen", the model compiler.
Al Davis, Gnucap Team (USA)
14:30-14:50 M8 SweepMe! - a modular, flexible, and versatile software platform for device characterization
Abstract
Device characterization is typically based on several measurement instruments that need to be controlled. Then, the ready-to-use software of each manufacturer does not help much as it cannot control the other instruments. As a consequence, one has to start programming. For many institutes and companies, it is not easy to create and maintain a characterization software that can quickly adapt to the needs of the current project and that is versatile enough to cover a wide range of tasks. Here, our measurement software SweepMe! (sweep-me.net) can be a way out. It provides a platform for combining modules of each instrument type, such as ‚SMU‘, ‚Wafer prober‘, ‚Network analyzer‘, or ‚LCRmeter‘. Equipment can be implemented via an open python interface and existing drivers are shared open-source. Once an instrument is implemented, even people with no or little programming skills can create characterization procedures like an on-wafer transistor testing in short time. All users create their procedures by combining and configuring our ready-to-use modules. Therefore, everybody benefits whenever content is improved or added. Our approach also fosters the interaction between institutes and companies in order to create common characterization procedures as a equipment can easily be interchanged. Additionally, we provide a package for the open-source community that allows to create own programs based on our drivers.
Axel Fischer, SweepMe!, Dresden (DE)
WED: 30.09.2020 (Virtual Room)
Session Chair: M. Schwarz, Bosch
 9:30-9:50 M9: Injection Barrier Modification by Organic Monolayers
Abstract
The energy level alignment between organic semiconductors and the respective (metal) electrodes in organic electronic devices is of key importance for efficient charge carrier injection. For many years, researchers have attempted to control this energy level alignment by means of functional self-assembled monolayers (SAMs) or the insertion of thin injection layers (made e.g. of doped organic semiconductors or pure dopants). An alternative to these approaches is the use of organic small molecule monolayers as contact primers which are deposited onto noble metal electrodes by means of vacuum deposition. We show that polar as well as non-polar phthalocyanines modify the work functions of clean Au(111) and Ag(111) surfaces as a function of their coverage and thus enable quantitative control of the metal work functions. This behaviour is successfully replicated for polycrystalline metal surfaces and it is found that full monolayers can even withstand air exposure.
A. A. Hauke, F. Widdascheck, G. Witte, Molecular Solid State Physics Group,
Philipps-Universität Marburg, Marburg (DE)
 9:50-10:10 M10 Quantitative Investigation of the Interplay between Intrinsic Transistor Noise and Circuit Nonlinearities
Abstract
The energy level alignment between organic semiconductors and the respective (metal) electrodes in organic electronic devices is of key importance for efficient charge carrier injection. For many years, researchers have attempted to control this energy level alignment by means of functional self-assembled monolayers (SAMs) or the insertion of thin injection layers (made e.g. of doped organic semiconductors or pure dopants). An alternative to these approaches is the use of organic small molecule monolayers as contact primers which are deposited onto noble metal electrodes by means of vacuum deposition. We show that polar as well as non-polar phthalocyanines modify the work functions of clean Au(111) and Ag(111) surfaces as a function of their coverage and thus enable quantitative control of the metal work functions. This behaviour is successfully replicated for polycrystalline metal surfaces and it is found that full monolayers can even withstand air exposure.
Leopold Van Brandt and Denis Flandre, UCL (B)
COFFEE BREAK
Session Chair: W.Grabinski, MOS-AK
10:50-11:10 M11: Emerging Devices: RFET and OPBT
Abstract
Reconfigurable field-effect transistors (RFETs) are devices for dynamically switching between n- and p-typepolarity which enables different logic computations using the samehardware. A simplified single-gate (SG) RFET design is presented which achieves the same functionality and dc characteristics as DG-RFET. Permeable Base Transistors (OPBTs) are of great interest for flexible electronic circuits as they offer very large on-current density and a record-high transition frequency. Stable and reproducible DC characteristics can be expectedand achieved regardless of statistical variation inthe fabrication of the base layer in OPBTs in terms of adeviation of pinhole diameter and density.
Gharder Darbandy, THM, Giessen, (D)
11:10-11:30 M12 Simulation and Modeling of Semiconductor Devices in MEMS
Abstract
In this paper the simulation and modeling of semiconductor devices in MEMS, by Bosch, one of the world’s largest supplier of micromechanical sensors in automotive and consumer applications, is briefly introduced. The simulation and modeling is one of the key elements to bridge the different domains between process technology, electronics, system and customers needs. The here presented methodology ensures an integration from various perspectives. Example of typical Sensor/MEMS design including various mechanical and electronical constraints is given.
Mike Schwarz, Robert Bosch GmbH (DE)
LUNCH
12:50-13:00 Opening IEEE EDS MINI COLLOQIUM
M. Schwarz, Bosch
Session Chair: A.Kloes, THM
13:00-13:45 MQ1: Analysis and modeling of OTFTs and IGZO TFTs from 150 to 350K
Abstract
TBD
Benjamin Iniguez, URV, (ES)
COFFEE BREAK
14:00-14:45 MQ2: Ultra-Thin Si Chips - A New Paradigm in Silicon Technology
Abstract
TBD
Joachim Burghartz, IMS-CHIPS (DE)
THU: 01.10.2020 (Virtual Room)
Session Chair: A.Kloes, THM
 9:00-9:45 MQ3: FOSS TCAD/EDA Tools for Advanced Compact Modeling
Abstract
Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes; thru the MOSFET, FDSOI, FinFET and TFET compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present two FOSS CAD simulation and design tools: ngspice and Qucs. Application and use of these tools for advanced IC design (e.g. analog/RF IC applications) directly depends the quality of the compact models implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the transistor level and then trigger further discussion on the compact/SPICE model Verilog-A standardization and development supporting FOSS CAD tools.
Wladek Grabinski, MOS-AK (EU)
COFFEE BREAK
Session Chair: Ghader Darbandy, THM
10:00-10:45 MQ4: 2D Electronics - Opportunities and Challenges
Abstract
During the past decade, 2D (two-dimensional) materials have attracted enormous attention from various scientific communities ranging from chemists and physicists to material scientists and device engineers. The rise of the 2D materials began in 2004 with the work on graphene done at Manchester University and Georgia Tech. Particularly the observed high carrier mobilities raised early expectations that graphene could be a perfect electronic material. It soon became clear, however, that due its zero bandgap graphene is not suitable for most electronic devices, in particular transistors. On the other hand, researchers have extended their work to 2D materials beyond graphene and the number of 2D materials under investigation is continuously rising. Many of these materials possess sizeable bandgaps and therefore may be useful for transistors. Indeed, the progress of research on 2D transistors has been rapid and MOSFETs with semiconducting 2D channels have been reported by many groups. A recent achievement was the demonstration of a 1-nm gate MoS2 MOSFET in 2016. Moreover, other types of 2D devices such 2D memristors, 2D sensors, and 2D devices optoelectronics are currently under investigation. In the present lecture, the most important classes of 2D materials are introduced and the potential of 2D transistors is assessed as realistically as possible. To this end, two key material properties – bandgap and mobility – are examined in detail and the mobility- bandgap tradeoff is discussed. The state of the art of 2D transistors is reviewed by summarizing relevant results of leading groups in the field and by comparing the performance of 2D transistors to that of competing conventional transistors. Based on these considerations, a balanced view of both the pros and cons of 2D transistors is provided and their potential in digital CMOS and in other domains of semiconductor electronics is discussed. It is shown that due to the rather conservative CMOS scaling scenarios described in the most recent ITRS and IRDS editions (compared to the more aggressive scenarios of previous ITRS editions), in the near-to-medium term it will be difficult for 2D materials to make inroads into mainstream CMOS. However, research on beyond-CMOS 2D devices has led to promising results. Exemplarily, the status and prospects of 2D sensors and 2D memristors is discussed.
Frank Schwierz, TU Ilmenau (DE)
COFFEE BREAK
11:00-11:45 MQ5: Stability and Reliability of 2D Transistors
Abstract
TBD
Tibor Grasser, TU Vienna, (AT)
LUNCH BREAK
12:50-13:00 Opening SYMPOSIUM SB MOS
M. Schwarz, Bosch and L. Calvet, Uni. Paris-Saclay
Session Chair: M. Schwarz, Bosch
13:00-13:30 SB1: Metal-Insulator-Graphene RF Diodes: From Devices to Integrated Circuits
Abstract
TBD
Zhenxing Wang, AMO (DE)
13:30-14:00
SB2: Schottky barrier devices for neuromorphic computing
Abstract
TBD
Laurie Calvet, Paris (FR), John Snyder (US), Mike Schwarz, NanoP (DE)
COFFEE BREAK
Session Chair: L. Calvet, Uni. Paris-Saclay
14:30-15:00

SB3: Nanowire metal-semiconductor heterostructures for functionality enhancement and quantum transport
Abstract
TBD
Walter Weber, TU Vienna (AT)
15:00-15:30 SB4: Schottky-type Contacts in Ultra-Short Channel Organic Semiconductor Devices for GHz-Operation
Abstract
Vertical organic transistors with a channel length of <300nm are ideally suited for high - frequency operation of flexible electronics devices. Here we present organic permeable base vertical organic transistors integrated into complementary circuits which show a rise and fall time of only 5ns in inverter circuit operating at <3V. These devices require high - quality Schottky - contacts to reach a high gain, device stability, and subthreshold slope.
Hans Kleemann, TU Dresden(DE)
15:30 CLOSING
Best papers of the Joint Spring MOS-AK Workshop and Symposium on Schottky Barrier MOS (SB-MOS) devices will be selected for a special Solid-State-Electronics (SSE) compact modeling issue of MOS-AK activities.

International MOS-AK Committee:
Committee
  • Local Organization Committee:
    • Prof. Dr.-Ing. Alexander Kloes; THM Giessen, NanoP (D)
    • Prof. Laurie Calvet, C2N, Palaiseau, (F)
    • Dr.-Ing. Mike Schwarz; Robert Bosch GmbH, NanoP (D)
      representing
      IEEE Region 8 - Western Europe Regional
      IEEE YP Germany
      IEEE Electron Devices Society
      IEEE EDS Compact Modeling Committee
  • International MOS-AK Board of R&D Advisers:
    • Larry Nagel, Omega Enterprises Consulting (USA)
    • Andrei Vladimirescu, UCB (USA); ISEP (FR)
  • MOS-AK Technical Committee:
    MOS-AK North America
  • Chair: Pekka Ojala, Exar Corporation (USA)
  • Co-Chair: Geoffrey Coram, Analog Devices (USA)
  • Co-Chair: Jamal Deen, U.McMaster (CA)
  • Co-Chair: Roberto Tinti, Keysight EEsof Division (USA)
    MOS-AK South America
  • Chair: Prof. Gilson I Wirth; UFRGS (BR)
  • Co-Chair: Prof. Carlos Galup-Montoro, UFSC (BR)
  • Co-Chair: Sergio Bampi, UFRGS (BR)
  • Co-Chair: Antonio Cerdeira Altuzarra, Cinvestav - IPN (MX)
  • Co-Chair: Roberto S. Murphy, INAOE (MX)
  • MOS-AK Europe
  • Chair: Ehrenfried Seebacher, AMS (A)
  • Co-Chair: Sanjay Mane, XFab (D)
  • Co-Chair: Benjamin Iniguez, URV (SP)
    MOS-AK Asia/South Pacific

  • Chair: Sadayuki Yoshitomi, Toshiba (J)
  • Co-Chair: A.B. Bhattacharyya, JIIT New Delhi (IN)
  • Co-Chair: Min Zhang, XMOD Tech, Shanghai (CN)
  • Co-Chair: Kaikai Xu, 电子科技大学 (CN)  
<
No.#4220
update:Sept.2020 (rev. F)
Contents subject to change ©1999-2020 All rights reserved. WG
Graphics © 2019 Oliver