Do we need standardization of the HV/LD MOS Transistor models and parameter sets?
Are HV/LD MOS Figures of Merit defined?
What are the most important effects which should be covered in HV/LD MOS models?
Capacitance modeling of HV/LD MOS devices
Self heating and topology dependent behavior
RF behaviour (are FT and FMAX values well defined?)
Trade off between minimizing RON and the device reliability/lifetime
Is convergence/reliability of the SPICE simulations an issue for HV/LD MOS transistors?
It
is very first attempt to rethink the HVMOS modeling and define a set of
initial tests, benchmarks, validations procedures which could be
summarized in an open, public domain documentation setting the HVMOS
modeling references. Your suggestions, ideas and thoughts on these
topics are appreciated. Please address your comments directly to Ehrenfried Seebacher.