MOS-AK/GSA India Workshop

Arbeitskreis MOS-Modelle und Parameterextraktion
MOS Modeling and Parameter Extraction Working Group
MOS-AK/GSA Workshop
March 16-18, 2012 India

MOS-AK: Enabling Compact Modeling R&D Exchange

In Collaboration with

INDIAN NATIONAL ACADEMY OF ENGINEERING

MOS-AK/GSA Workshop Sponsors

Platinium Sponsors

Gold Sponsors

Silver Sponsors

Technical MOS-AK/GSA Program Promoters

The MOSIS Services

Technical Workshop Program

Venue:	Jaypee Institute of Information Technology (JIIT), A-10, Sector-62, Noida (U.P.), India Phone: 0120-2400973-976, 2400987
Registration:	To register please visit the INAE website and complete the registration form
Important Dates:	1st Announcement and Call for Papers - Q4 2011 on-line poster abstract submission deadline - Jan. 31, 2012 Final Workshop Program - Feb. 20, 2012 MOS-AK/GSA Workshop - March 16-18, 2012
Synopsis:	HiTech forum to discuss the frontiers of electron device modeling with emphasis on simulation-aware models. MOS-AK/GSA Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/Spice modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme - frontiers of the compact modeling for nm-scale MEMS designs and CMOS/SOI circuit simulation. The specific workshop goal will be to classify the most important directions for the future development of the electron device models, not limiting the discussion to compact models, but including physical, analytical and numerical models, to clearly identify areas that need further research and possible contact points between the different modeling domains. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe) who are interested in device modeling; ICs designers (RF/Analog/Mixed-Signal/SoC) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind the IC simulation in modern device models.
	Technical Workshop Program
	March 16, 2012: MOS-AK/India Workshop
Time	Program
08:30-09:30	On-Site Registration
09:30-10:30	Inaugural Session and Launching of MOS-AK/GSA, India
10:30-13:30	Technical Session: I
I-1	Surface Potential Based Modeling: HiSIM Compact Model Family Mitiko Miura-Mattausch, Hiroshima University, Japan
I-2	Hardware Accelerated Interconnect Capacitance Extractor for VLSI Design Narain D. Arora, Silterra, Malaysia
I-3	BSIM Modeling Roadmap Yogesh Chauhan, UC Berkeley, USA
I-4	Unification of MOS-compact models with the unified regional modeling approach/ Compact model application to statistical variability and reliability studies Xing Zhou, NTU, Singapore
	MOS-AK/GSA Poster Session
13:30-14:30	Lunch
14:30-17:30	Technical Session II
II-1	MOSFET Compact Modeling Extensions for Circuit Simulation: A perspective from Industry Andre Juge (STM), France
II-2	Benchmarking of High Voltage (HV) MOS Transistor Models Ehrenfried Seebacher, AMS, Austria
II-3	High Voltage (HV) MOSFET Technology Models & Applications Vaidyanathan Subramanian, IBM, India
II-4	General Methodology to Develop Statistical Compact MOSFET Models for VLSI Circuit Simulation Samar Saha, University of Colorado, USA
19:00-21:00	Networking Dinner
	March 17, 2012: MOS-AK/India Workshop
Time	Program
09:30-11:30	Technical Session III
III-1	Verilog-A Compact Model Standardization Wladek Grabinski, MOS-AK/GSA, EU
III-2	SPICE to QucsStudio via Qucs: An international attempt to develop a freely available GPL RF design, compact modeling, simulation, data processing and manufacturing development environment for engineers Mike Brinson, London Metropolitan University, UK
III-3	An Automatic Parameter Extraction Procedure for an Explicit Surface Potential Based Compact Double Gate MOSFET model Thomas Gneiting, ADMOS, Germany
III-4	Insights into the Design and Optimization of Tunnel-FET Devices and Circuits for Future Ultra Low Power Applications V Ramgopal Rao, IIT Mumbai, India
11:30-13:30	Technical Session IV
IV-1	Surface Acoustic Wave Device/Sensor Modeling for SPICE Simulation A.B.Bhattacharyya, JIIT Noida, India
IV-2	Incorporation of Quantum Mechanical Effects in Compact Models of Bulk MOSFETs Amitava Dasgupta, IIT Chennai, India
IV-3	RF-SOI modeling RF front end modules Tamilmani Ethirajan, IBM, India
IV-4	indDG: A New Compact Model for Independent Double Gate Transistor Shantanu Mahapatra, IISc, India
13:30-14:30	Lunch
14:30-16:30	Technical Session V
V-1	BSIM6 Symmetric Bulk MOSFET Model Yogesh Chauhan, UC Berkeley, USA
V-2	Compact modeling of SOI Drain Extended MOSFET (DEMOS) including High-voltage and Floating Body Effects M.Jagdesh Kumar, IIT Delhi, India
V-3	Compact Modeling: Graphene Transistors Navakanta Bhat, IISC Bangalore, India
V-4	Performance Modeling, Parameter Extraction Technique and Statistical Modeling of Nano-scale CMOS Transistors for VLSI Circuit Simulation Soumya Pandit, IRPE, Kolkata, India
16:30-17:30	Valedictory Function
	March 18, 2012: MOS-AK/India Tutorial
	CMOS technology and SPICE Models Dr. N.D. Arora, Silterra, Malaysia
8.30	Introductory address: Prof. AB Bhattacharyya
9:00-10:30	MOS Transistors Models (1.5h)
11:00-12:30	SPICE models for advanced CMOS chip design (1.5h):
14:00-17:00	Interconnect modeling (3.0h)
	MOS-AK India Committee
Committee:	International Advisory Committee: A.B. Bhattacharyya, Emeritus Professor, JIIT, India (Chair) S.C. Saxena, Vice Chancellor, JIIT, Noida (Host) Ehrenfried Seebacher, austriamicrosystems AG, Austria (Co-Chair) Wladek Grabinski, MOS-AK (European Arrangements Co-Chair) M.J. Zarabi, Chairman, Vice-President, Microelectronics Forum INAE New Delhi, India K.D. Nayak, DRDO, New Delhi Andre Juge, ST Microelectronics, France Vinod Menzes, TI, India Narain D Arora, Silterra, Malaysia Vivek Sharma, ST Microelectronics, India Ganesh Guruswamy, Freescale, India Vipin Madangarli, IBM, India Abhishek Dixit, IBM, India Vijay Kumar Ivaturi, Wipro Limited, India Jyotirmoy Daw, Mentor Graphics, Noida Jaswinder Ahuja, Cadence, Noida Pradip K Dutta, Synopsys, India & Chairman, ISA, India Praveen Vishakantaiah, Intel, India Juzer Vasi, IIT, Mumbai Ramgopal Rao, IIT, Mumbai Navkant Bhat, IISC, Bangaluru S. Koul, IIT, Delhi Amitava Dasgupta, IIT, Madras Y. Medury, JIIT, India Organizing MOS-AK/GSA Committee: A.B. Bhattacharyya, Emeritus Professor, JIIT, India (Chair) S.C. Saxena, Vice Chancellor, JIIT, Noida (Host) Ehrenfried Seebacher, austriamicrosystems AG, Austria (Co-Chair) Wladek Grabinski, MOS-AK (European Arrangements Co-Chair) M.J. Zarabi, Chairman, Vice-President, Microelectronics Forum INAE New Delhi, India Varambally Rajamohan, ST Microelectronics, India Shantanu Mahapatra, IISc, India Rajamohan Varambally, ST Microelectronics, Noida, India Kulbhushan Misri, Freescale, Noida, India M. Jagdesh Kumar, IIT Delhi, India Manoj Saxena, Delhi University, South Campus, New Delhi, India Extended MOS-AK/GSA Committee: Chelsea Boone, GSA Director of Research Wladek Grabinski, GMC Suisse; MOS-AK/GSA Group Manager MOS-AK/GSA North America: Chair: Pekka Ojala, Exar Corporation Geoffrey Coram, Analog Devices Jamal Deen, U.McMaster Roberto Tinti, Agilent EEsof Division MOS-AK/GSA South America: Chair: Gilson I Wirth; UFRGS; Brazil Carlos Galup-Montoro, UFSC; Brazil Sergio Bampi, UFRGS, Brazil Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico MOS-AK/GSA Europe: Chair: Ehrenfried Seebacher, austriamicrosystems AG Alexander Petr, XFab Benjamin Iniguez, URV James Victory, Sentinel-IC MOS-AK/GSA Asia/Pacific: Chair: Goichi Yokomizo, STARC, Japan Sadayuki Yoshitomi, Toshiba, Japan A.B. Bhattacharyya, JIIT, India Xing Zhou, NTU, Singapore

No.# 1855

update: Feb. 2012 (rev. f)