MOS-AK India
Calendar Submission Registration Committee About Hyderabad
MOS-AK: Enabling Compact Modeling R&D Exchange
MOS-AK/India Sponsors and Technical Program Promoters

IIT Hyderabad
Workshop Host
Platinum Sponsor
Gold Sponsor
Synergy Measuremetns
Rohde & Schwarz

Silver Sponsors
Semi-Conductor Laboratory (SCL)

MOS-AK Technical Program Promoters
IEEE CAS EDS IESA Swissnex India
powered by
Europractice TNL
Technology of Next Level
Driven by Innovation

MOS-AK Confernce is an open intenational event and all Prospective Sponsors are welcome to join us at IIT Hyderlabad.
Attached file under the link details all available sponsorship options.
MOS-AK/India Final Program
Important Dates:
  • Call for Papers - 1 Sept. 2018
  • 2nd Announcement -  1 Oct. 2018
  • Paper and Tutorial Submission Deadline - 30 Nov. 2018
  • Notification of Acceptance - 15 Jan. 2019
  • Camera Ready Paper Submission - 28 Jan. 2019
  • Registration and Final Conference Program - 15 Jan. 2019
  • MOS-AK/India Conference - February 24-27, 2019
    • Feb. 24      - IEEE EDS DL-MQ on Compact Modeling
    • Feb. 25      - ONE day SPICE/Verilog-A Modeling Tutorials
    • Feb. 26-27 - TWO days SPICE/Verilog-A Modeling Conference
Indian Institute of Technology (IIT)
Hyderabad, Kandi
Telangana State, India
registration (any related enquiries can be sent or call 9652158557)
Registration Type
IEEE member
Non IEEE member
Students - Tutorial Only - 1 day registration
Rs. 1000
Rs. 1250
Students - Tutorial and Conference – 3 day registration
Rs. 2000
Rs. 2500
Professionals - Tutorial Only – 1 day registration
Rs. 1500
Rs. 2000
Professionals - Tutorial and Conference – 3 day registration
Rs. 3000 Rs. 3500

Student Registrations (UG/PG/Ph.D) will have to produce their valid ID card at registration desk. The above registration consists of Lunch, Snacks, Registration Kit and Participation Certificate. Fees is non refundable and non transferable.

Limited Accommodation available at IIT Hyderabad Campus on payment of nominal charges. For details please send email to

Registration is only Online through secure payment gateway of Explara. Please visit
DAY-0 Monday, 25 February 2019
Venue: C- LH3, IIT Hyderabad
9:00 - 10:00 Registrations
TRACK - A (Venue: C LH3) TRACK - B (Venue: C- LH 8)
10:00 - 11:30
Tutorial A1

Speaker: Dr. Charvaka Duvvury
iT2 Technologies (USA)

Topic: ESD on-chip protection design
10:00 - 11:15
Tutorial B1

Speaker: Dr. Wladek Grabinski

Topic: Verilog-A Standardization
11:15 - 11:30 TEA BREAK 11:15 - 11:30 TEA BREAK
11:30 - 12:30
Tutorial A1 (Contd)

Speaker: Dr. Charvaka Duvvury
iT2 Technologies (USA)

Topic:ESD on-chip protection design
11:30 - 12:30
Tutorial B1 (Contd)

Speaker: Dr. Wladek Grabinski

Topic:Verilog-A Standardization
12.30 - 1:30 LUNCH BREAK 12.30 - 1:30 LUNCH BREAK
1:30 - 3:00
Tutorial A2

Speaker: Weronika Zubrzycka, AGH, Poland
Topic:Radiation effect and Radiation hardening in devices
1.30 - 3:00
Tutorial B2

Speaker: Prof. Roberto Murphy

Topic:Characterization of Semiconductor Devices in the High Frequency Regime
3:00 - 3:15 TEA BREAK 3:00 - 3:15 TEA BREAK
3.15 - 4.15
Tutorial A2 (Contd)

Speaker: Weronika Zubrzycka, AGH, Poland
Topic:Radiation effect and Radiation hardening in devices
3.15 - 4.15
Tutorial B2 (Contd)
Speaker: Prof. Roberto Mu

Topic: Characterization of Semiconductor Devices in the High Frequency Regime
DAY-1 Tuesday, 26 February 2019
Venue: C- LH3, IIT Hyderabad
9:00 - 10:20 Registrations
10:20 - 11:00
Keynote Talk

Speaker: Prof. Yogesh Singh Chauhan, IIT Kanpur
Topic: Negative Capacitance Transistors - Modeling, Simulation and Processor Performance
11:00 - 11:15
11:15 - 12:00
Plenary Talk

Speaker: Prof. Jaijeet Roychowdhury, UC, Berkeley, USA
Topic: Well-Posed Compact Modeling
12:40 - 1:25 LUNCH BREAK
 1:25 - 2:10

1:25 - 1:40 


1:40 - 1:55

1:55 - 2:10
Paper Session
Parallel Tracks - A(3 - 33,20,35) and B(3 - 50,14,57)
Track A venue: C - LH10Track B Venue: C - LH11
Track A- ams Semiconductors Track Track B - Rhode and Schwarz Track
P- ID Author Title P-ID Author Title
33 Chithra Modeling Techniques for Faster Verification of a Time to Digital Converter System-on-Chip Design 50 Praveen Pal Comparative analysis of oxides to improve performance of DC-MOS-HEMTs
Hanumantha Rao G.
A 0.5 V, 1 nA Switched Capacitor PTAT Current Reference Circuit 14 NavjeetBagga Demonstration of a Novel Ferroelectric-Dielectric Negative Capacitance Tunnel FET
35 Ravi Kumar Adusumalli  A simple flip-around switch technique to mitigate charge injection modeling inaccuracies in high precision switched-capacitor circuits 57 Roji Marjorie 2 D analysis of self aligned LDMOS structures in terms of breakdown voltages
2:10 - 2:50
Keynote Talk

Speaker: Prof. Manoj Saxena, IEEE EDS, Delhi
Topic:Modeling and Simulation of Tunnel Field Effect Transistor as a Biosensor
2:50 - 3:00 TEA BREAK
3:00 - 3:40

Keynote Talk

Speaker: Weronika Zubrazycka, AGH, Poland
Topic: Radiation Effects on Circuits for Space and High-Energy Physics Applications - A case study
3:40 - 4:20

Keynote Talk

Speaker: Dr. Usha Gogineni, Maxim semiconductors
Topic: Compact Models for Analog and Mixed Signal Design
4:20 - 5:00
Screen Clipping
Panel Discussion

Speaker: Dr. Latha Christie, DRDO, Bangalore
Topic:Challenges and opportunities for women in Engineering.
DAY-2 Wednesday, 27 February 2019
  Venue: C- LH8, IIT Hyderabad
9:00 - 10:00 Registrations
10:00 - 11:00

10:00 - 10:15


10:15 - 10:30

10:30 - 10:45


10:45 - 11:00
Paper Session
Parallel Tracks C(4 - 29,19,58,59) and D(4-34,31,47,61)
Track C venue:C LH8Track D Venue: C LH10
Track C: Synergy Track Track D: SCL Track
P-ID Author Title P-ID Author Title
29 Ashwani Kumar Verilog-A SPICE Model of PECVD SiO2 OTP Memory Device
34 Mohit D. Ganeriwala A Compact Charge and Surface Potential Model for III-V Quadruple-Gate FETs With Square Geometry
19 chitrakantsahu GAA 3D Si-MOSFET Hybrid Biosensor with Integrated Amplifier and Noise Cancellation Stage 31 Jhansirani Jena Performance Evaluation of Gate-All-Around Si Nanowire Transistors with SiGe Strain engineering
58 Archana Study of CNTFET Based Pattern Recognition Circuits in Comparison With CMOS Technology 47 Suresh Balanethiram
Shubham Pande
Development of Low-Cost Silicon BiCMOS Technology for RF Applications
59 Vikash Kumar Analysis and Compact Modeling of Drain-Extended FinFET
61 Sheikh Aamir Ahsan Impact of Via-Inductance on Stability Behavior of Large Gate-Periphery Multi-finger RF Transistors
11:00 - 11:15 TEA BREAK
11:15 - 12:00
Plenary Talk

Speaker: Dr. Ehrenfried Seebacher, ams(A)
Topic: Compact Modeling for Industrial Applications
12:00 - 12:40
Keynote Talk

Speaker: Madabusi Govindrajan, GLOBALFOUNDRIES, Bangalore
Topic: Challenges for RF modeling in the connected era
12:40 - 1:30 LUNCH BREAK
1:30 - 2:30

1:30 - 1:45


1:45 - 2:00


2:00 - 2:15


2:15 - 2:30
Paper Session
Parallel Tracks E(5- 24,23,60,27) and F(5-16,43,25,37)
Track E venue: C LH3Track F Venue: C LH8
Track E: Synopsys Track Track F: Xilinx Track
P- ID Author Title P- ID Author Title
24 Susmitha Kothapalli Optimization of electrical characteristics of Tunnel FET incorporating Gate Engineering
16 Rishabh Booshan Theoretical Modeling and Numerical Simulation of Elliptical Capacitive Pressure Microsensor
23 Skandha Deepsita S Energy Efficient Binary Adders for Error Resilient Applications
43 Seshadri Reddy Capacitance Modelling of Multilayer Perforated Electrodes for Dielectric Elastomer Actuator Applications
60 Jay Hind Kumar Verma Simulation, Characterization and Parameter Extraction of Radiation Hardened MOSFET
25 Sreenath Ak
Reconfigurable Math Accelerator for ultra-low power sensing workloads on IoT edge devices
27 Eleena Mohapatra Strain Engineering in AlGaN/GaN HEMTs for Performance Enhancement
37 Tridip Sarma Effect of Leakage Currents in Adiabatic Logic Circuits at Lower Technology Nodes
2:30 - 3:10
Keynote Talk

Speaker: Prof. Santanu Mahapatra, IISc, Bangalore
Topic: Atom-to-Circuit modeling technique for emerging nanomaterial based MOSFETs
3:10 - 3:25 TEA BREAK
3:25 - 4:15
Screen Clipping
Keynote Talk

Speaker: Prof. Gilson Wirth, UFRGS (Webinar)
Topic: Charge Trapping Phenomena in MOSFETS: From Noise to Bias Temperature Instability
4:15 - 4:45 CLOSING

Original unpublished works in topics related to the following areas (but not limited to) can be submitted for publication. The proceedings of the conference will be submitted to IEEE Explore. Best Paper Award: Gold leaf, Silver leaf and Bronze leaf certificates will be given to best papers.

Highest Ranked papers from regular submission will be invited to extend their paper in the form of a book chapter. All these submission will be published in the form of a book titled "Compact Modeling: Technology, Devices, IC Design" by River Publishers, the technical program promoter of MOS-AK/India 2019 Conference.

International MOS-AK Committees:
  • Steering Committee
    Ehrenfried Seebacher, ams (A)
    A.B. Bhattacharyya, FNA,FNAE
    M.J. Zarabi, Retd. Director, SCL, India
    M.K. Radhakrishnan, Chair, IEEE EDS, Asia Pacific
    U.B. Desai, Director, IIT Hyderabad
    Anilkumar Muniswamy, Chair, IESA
    Sebastien Hug, Consul General and CEO swissnex
    V. Hanuma Sai, AMS Semiconductors Pvt. Ltd.
    Rajeev Joshi, IBM, USA
    Ramgopal Rao, IITD, Delhi
    Navkanth Bhat, IISc, Bangalore
    Yogesh Chauhan, IIT, Kanpur
    Santanu Mahapatra, IISc, Bangalore
    Vipin Mandangarli, Global Foundries
    Venkatnarayan Hariharan, Intel Bangalore
    C.P. Ravikumar, Texas Instruments, Bangalore
    PVS Maruthi Rao, IEEE Hyderabad Section
    Abha Jain, Cadence, India
    Merugu Lakshminarayana, IEEE Hyderabad Section
    Manoj Saxena, IEEE Electron Devices Society

  • Organizing Committee
  • General Co-Chairs
    PA Govindacharyulu, IEEE CAS/EDS, Hyderabad Section
    Wladek Grabinski, MOS-AK (EU)
  • Organizing Co-Chairs
    Sushmee Badhulika, IITH
    A.G. Krishnakanth, AMS Semiconductors Pvt. Ltd.
  • TPC Co-Chairs
    PV Anand Mohan, IEEE CAS, Bangalore Section
    N Venkatesh, Redpine Signals
  • Publication Co-Chairs
    Asudeb Dutta, IITH
    Wladek Grabinski, MOS-AK (EU) 
  • Finance Chair
    Arif Sohel, IEEE CAS/EDS, Hyderabad Section
  • Tutorial Co-Chairs
    Kaleem Fatima, IEEE CAS/EDS, Hyderabad Section
    Ghanshyam Krishna, University of Hyderabad
  • Publicity Co-Chairs
    Anurag Mangla, ams (A)
    P. Chandrasekhar, IEEE CAS/EDS, Hyderabad Section
  • Industry Liaison Co-Chair
    Sabat L Samrat, University of Hyderabad
    Vijaya Sankar Rao, University of Hyderabad
  • Sponsorships Co-Chairs
    Avinash Yadlapati, Mirafra Technologies
    Satish Maheshwaram, NIT Warangal
  • Exhibition Co-Chairs
    Aftab Hussain, IIIT Hyderabad
    Shivam Verma, NIT Warangal
  • Local Arrangement Co-Chairs
    Gajendranath, IITH
    M.A. Raheem, IEEE CAS/EDS, Hyderabad Section
  • MOS-AK Technical Committee
    MOS-AK North America
  • Chair: Pekka Ojala, Exar Corporation
  • Co-Chair: Geoffrey Coram, Analog Devices
  • Co-Chair: Prof. Jamal Deen, U.McMaster
  • Co-Chair: Roberto Tinti, Keysight EEsof Division
    MOS-AK South America
  • Chair: Prof. Gilson I Wirth; UFRGS; Brazil
  • Co-Chair: Prof. Carlos Galup-Montoro, UFSC; Brazil
  • Co-Chair: Sergio Bampi, UFRGS, Brazil
  • Co-Chair: Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
    MOS-AK Europe
  • Chair: Ehrenfried Seebacher, AMS, Austria
  • Co-Chair: Suba Subramaniam, XFab, XFab, Germany
  • Co-Chair: Prof. Benjamin Iniguez, URV, Spain
  • Co-Chair: Franz Sischka, SisConsult, Germany
    MOS-AK Asia/South Pacific

  • Chair: Sadayuki Yoshitomi, Toshiba (J)
  • Co-Chair: A.B. Bhattacharyya, JIIT New Delhi (IN)
  • Co-Chair: Min Zhang, XMOD Technologies, (CN)
  • Co-Chair: Kaikai Xu, 电子科技大学 (CN)  
  • Co-Chair: Xing Zhou, NTU Singapore (SG)  
update: May 2018 (rev. A)
Contents subject to change 1999-2019 All rights reserved. WG
Graphics 2019 Oliver