MOS-AK India 
Calendar Submission Registration Committee About Hyderabad
Technical MOS-AK Program Promoters
MOS-AK: Enabling Compact Modeling R&D Exchange
IIT Hyderabad
Workshop Host
Swissnex India

Semi-Conductor Laboratory (SCL)

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MOS-AK Confernce is an open intenational event and all Prospective Sponsors are welcome to join us at IIT Hyderlabad.
Attached file under the link details all available sponsorship options.
MOS-AK Call for Papers
Important Dates:
  • Call for Papers - 1 Sept. 2018
  • 2nd Announcement -  1 Oct. 2018
  • Paper and Tutorial Submission Deadline - 30 Nov. 2018 (Hard Deadline)
  • Notification of Acceptance - 30 Dec. 2018
  • Registration and Camera Ready Paper Submission - 10 Jan. 2019
  • Final Conference Program - 15 Jan. 2019
  • MOS-AK/India Conference - February 24-27, 2019
    • Feb.24      - IEEE EDS DL-MQ on Compact Modeling
    • Feb.25      - ONE day SPICE/Verilog-A Modeling Tutorials
    • Feb 26-27 - TWO days SPICE/Verilog-A Modeling Workshop
Indian Institute of Technology (IIT)
Hyderabad, Kandi
Telangana State, India
registration (to be open in Jan. 2019; any related enquiries can be sent
   Synopsis and Workshop Topics
  • HiTech forum to discuss the frontiers of electron device modeling with emphasis on simulation-aware compact/SPICE models.
  • MOS-AK Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/Spice modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme - frontiers of the compact modeling for nm-scale MEMS designs and CMOS/SOI circuit simulation.
  • The specific workshop goal will be to classify the most important directions for the future development of the electron device models, not limiting the discussion to compact models, but including physical, analytical and numerical models, to clearly identify areas that need further research and possible contact points between the different modeling domains. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe) who are interested in device modeling; ICs designers (RF/Analog/Mixed-Signal/SoC) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind the IC simulation in modern device models.
Topics: to be covered include the following:
Compact Modeling Track 
Circuits and Systems Track 
  • Advances in semiconductor technologies and processing
  • Compact Modeling (CM) of the electron devices
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • FOSS TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT and SOI-based memory cells
  • Organic, Bio/Med devices/technology modeling
  • Microwave, RF device modeling, HV/Power device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D reliability/ageing, DFY, DFT
  • Foundry/Fabless Interface Strategies
  • Analog Circuits
  • Biomedical and Life-Science Circuits, Systems and Applications
  • Circuits and Systems for Communication
  • Emerging Technologies for Circuits and Systems
  • HP/HV IC Designs
  • Memory Circuits and Systems
  • Mixed Signal Circuits
  • RF/mm-Wave IC Design and Technology
  • Sensory Systems System-on-Chip and CAD
  • Testing Technology
  • VLSI Systems & Applications
  • And any other IC design related topic
Speakers (tentative alphabetic list):
Prof. Yogesh Singh Chauhan, IIT Kanpur
Dr. Siddhartha Dhar, STM, Noida
Prof. Charvaka Duvvury, iT2 Technologies, Dallas, USA
Dr. Madabausi Govindrajan, GlobalFoundries, Bangalore
Dr. Wladek Grabinski, MOS-AK (EU)
Dr. Venkatnarayan Hariharan, Intel, Bangalore
Prof. Santanu Mahapatra, IISc, Bangalore
Prof. Roberto Murphy, INOE, Mexico
Prof. Jaijeet RoyChaudhary, UC, Berkeley, USA
Prof. Manoj Saxena, IEEE EDS, Delhi
Dr. Ehrenfried Seebachar, ams, Austira
Prof. Gilson Wirth, UFRGS, Brazil
Abstract Submission (any related enquiries can be sent to

Original unpublished works in topics related to the following areas (but not limited to) can be submitted for publication. The proceedings of the conference will be submitted to IEEE Explore. Best Paper Award: Gold leaf, Silver leaf and Bronze leaf certificates will be given to best papers.

Highest Ranked papers from regular submission will be invited to extend their paper in the form of a book chapter. All these submission will be published in the form of a book titled "Compact Modeling: Technology, Devices, IC Design" by River Publishers, the technical program promoter of MOS-AK/India 2019 Conference.
Author Instruction and Registration Details

International MOS-AK Committee:
  • Steering Committee
    Ehrenfried Seebacher, ams (A)
    A.B. Bhattacharyya, FNA,FNAE
    M.J. Zarabi, Retd. Director, SCL, India
    M.K. Radhakrishnan, Chair, IEEE EDS, Asia Pacific
    U.B. Desai, Director, IIT Hyderabad
    Anilkumar Muniswamy, Chair, IESA
    Sebastien Hug, Consul General and CEO swissnex
    V. Hanuma Sai, AMS Semiconductors Pvt. Ltd.
    Rajeev Joshi, IBM, USA
    Ramgopal Rao, IITD, Delhi
    Navkanth Bhat, IISc, Bangalore
    Yogesh Chauhan, IIT, Kanpur
    Santanu Mahapatra, IISc, Bangalore
    Vipin Mandangarli, Global Foundries
    Venkatnarayan Hariharan, Intel Bangalore
    C.P. Ravikumar, Texas Instruments, Bangalore
    PVS Maruthi Rao, IEEE Hyderabad Section
    Abha Jain, Cadence, India
    Merugu Lakshminarayana, IEEE Hyderabad Section
    Manoj Saxena, IEEE Electron Devices Society

  • Organizing Committee
  • General Co-Chairs
    PA Govindacharyulu, IEEE CAS/EDS, Hyderabad Section
    Wladek Grabinski, MOS-AK (EU)
  • Organizing Co-Chairs
    Sushmee Badhulika, IITH
    A.G. Krishnakanth, AMS Semiconductors Pvt. Ltd.
  • TPC Co-Chairs
    PV Anand Mohan, IEEE CAS, Bangalore Section
    N Venkatesh, Redpine Signals
  • Publication Co-Chairs
    Asudeb Dutta, IITH
    Wladek Grabinski, MOS-AK (EU) 
  • Finance Chair
    Arif Sohel, IEEE CAS/EDS, Hyderabad Section
  • Tutorial Co-Chairs
    Kaleem Fatima, IEEE CAS/EDS, Hyderabad Section
    Ghanshyam Krishna, University of Hyderabad
  • Publicity Co-Chairs
    Anurag Mangla, ams (A)
    P. Chandrasekhar, IEEE CAS/EDS, Hyderabad Section
  • Industry Liaison Co-Chair
    Sabat L Samrat, University of Hyderabad
    Vijaya Sankar Rao, University of Hyderabad
  • Sponsorships Co-Chairs
    Avinash Yadlapati, Mirafra Technologies
    Satish Maheshwaram, NIT Warangal
  • Exhibition Co-Chairs
    Aftab Hussain, IIIT Hyderabad
    Shivam Verma, NIT Warangal
  • Local Arrangement Co-Chairs
    Gajendranath, IITH
    M.A. Raheem, IEEE CAS/EDS, Hyderabad Section
  • MOS-AK Technical Committee
    MOS-AK North America
  • Chair: Pekka Ojala, Exar Corporation
  • Co-Chair: Geoffrey Coram, Analog Devices
  • Co-Chair: Prof. Jamal Deen, U.McMaster
  • Co-Chair: Roberto Tinti, Keysight EEsof Division
    MOS-AK South America
  • Chair: Prof. Gilson I Wirth; UFRGS; Brazil
  • Co-Chair: Prof. Carlos Galup-Montoro, UFSC; Brazil
  • Co-Chair: Sergio Bampi, UFRGS, Brazil
  • Co-Chair: Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
    MOS-AK Europe
  • Chair: Ehrenfried Seebacher, AMS, Austria
  • Co-Chair: Suba Subramaniam, XFab, XFab, Germany
  • Co-Chair: Prof. Benjamin Iniguez, URV, Spain
  • Co-Chair: Franz Sischka, SisConsult, Germany
    MOS-AK Asia/South Pacific

  • Chair: Sadayuki Yoshitomi, Toshiba (J)
  • Co-Chair: A.B. Bhattacharyya, JIIT New Delhi (IN)
  • Co-Chair: Min Zhang, XMOD Technologies, (CN)
  • Co-Chair: Kaikai Xu, 电子科技大学 (CN)  
  • Co-Chair: Xing Zhou, NTU Singapore (SG)  
update: May 2018 (rev. A)
Contents subject to change 1999-2018 All rights reserved. WG
Graphics 2017 Oliver