Arbeitskreis MOS-Modelle und Parameterextraktion
MOS Modeling and Parameter Extraction Working Group
MOS-AK/ESSDERC/ESSCIRC Workshop
Compact Modeling for Nano CMOS/SOI Technologies

Friday, 14 September 2007 in Munich
Workshop Agenda: Friday, 14 September 2007 in Munich
Workshop Chair: W.Grabinski
Technical Program Coordinator: Prof. H. Iwai 
  • Morning Session
    • 9:00-11:00 Oral presentations
    • 10:00-10:30 (coffee break)
  • Poster Session
    • 11:30-12:00 Posters
    • 12:00-13:00 (lunch)
  • Afternoon Session
    • 13:00-16:00 Oral presentations
    • 14:30-15:00 (coffee break)
Sponsors of the MOS-AK Workshop
Agilent AMS
Tanner
Synopsys XFab TUM
Technical Program Promoters
EuroTraining FSA 
ijnm_wiley SiliconSaxony
Compact Modeling for Nano CMOS/SOI Technologies - Workshop Program
Display Format: Citation Citation & Abstract
9:00 Workshop Opening:
9:00-11:30 Morning Session - Chair: Prof. G. Baccarani
Keynote:  Impact of Digital MOS Scaling on Circuit Performance and Related Compact Modeling Challenges
Prof. Robert W. Dutton, Stanford University
  Modelling and Parameter Extraction Experiences with PSP: An Advanced Surface-Potential-Based MOSFET Compact Model for Circuit Simulation
Joachim Assenmacher, Infineon
  Accuracy and Speed Performance of HiSIM Versions 231 and 240
H.J. Mattausch, M. Miura-Mattausch, N. Sadachika, M. Miyake, T. Iizuka, T.Ohguro, Y. Furui1
Hiroshima University and 1STARC
  Tools for Model-based Design and Test
Alan Mantooth and Martin Vlach, University of Arkansas/Lynguent:
11:30-12:00 Poster Session - Chair: W.Grabinski
12:00-13:00 Lunch:
13:00-16:00 Afternoon Session - Chair: Dr. N. Itoh
  Small-signal Modelling of SOI-specific MOSFET Behaviours
Denis Flandre, UCL Louvain
  Modeling Flash Memories for IC Designs
Luca Larcher,  Universitą di Modena e Reggio Emilia
 star TRADICA Modeling Environment
Kai E. Moebus, TU Dresden
  Modeling 32 V Asymmetric LDMOS Using Hspice Level 66
Alhan Farhanah Abd Rahim1,2, Mohd Shahrul Amran1 and Albert Victor Kordesch1
1Silterra Malaysia, 2Universiti Teknologi MARA
 star Circuit-level Modeling of Carbon Nanotube Field Effect Transistors
Tom J. Kazmierski, University of Southampton
  End of the MOS-AK Workshop
star recommended papers for further IJNM publication
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No.#10902
update: 22-Sept-07 (rev.c)
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