IEEE MOS-AK/GSA Workshop in Rome

Arbeitskreis MOS-Modelle und Parameterextraktion
MOS Modeling and Parameter Extraction Working Group
MOS-AK/GSA Workshop
April 8-9, 2010 Sapienza Università di Roma

MOS-AK 2010: over 20 Years of Enabling Compact Modeling R&D Exchange

MOS-AK/GSA Workshop's Organizers and Sponsors

Technical MOS-AK/GSA Program Promoters


	The MOSIS Services

MOS-AK/GSA Publication Partners

Final MOS-AK/GSA Rome Program

Free on-line registration

Venue:

The Faculty of Engineering, Sapienza Università di Roma, Via Eudossiana 18, Rome

Map

Recommended Hotels:

The hotels at the link below have an agreement with "La Sapienza";
http://www.uniroma1.it/organizzazione/postaeservizi/servizipersonale/risorse/default.php
Hotel Palatino http://www.hotelpalatino.com/

Other hotels (a short list):

Best Western Hotel Globus Rome http://www.globushotelrome.it/
Hotel Felice in San Lorenzo area http://www.hotelfelice.com/en/home.html
Hotel Laurentia http://www.hotellaurentia.com/index.php

Display Format:

Citation

Citation & Abstract

10:30

April 8 - Plenary Session - Chair: F. Irrera

T_1

Workshop Opening and Welcome
F. Irrera, F. Famà, R. Tinti and W.Grabinski
Workshop Organizing Committee

T_2

Compact Modeling of Nanoscale Transistors
Giuseppe Iannaccone
Università degli Studi di Pisa

T_3

Modeling of Electrostatics and Drain Current in Nanoscale Quadruple Gate MOSFET Using Conformal Mapping Techniques
Udit Monga, Dag-Martin Nilsen and Tor A. Fjeldly
Department of electronics and Telecommunications, Norwegian University of Science and Technology, and University Graduate Center, Norway

T_4

MOSFET Compact Modeling for Design of Mixed Analog/Digital Circuits at Cryogenic Temperature
Patrick Martin
CEA, LETI, MINATEC, Grenoble (F)

T_5

Compact Models of Non Volatile Memories for Variability Evaluation
Andrea Marmiroli
Numonyx (I)

12:30

Lunch

14:00-19:00

Visit Micron Technology at Avezzano

9:00

April 9 - Morning Session - Chair: M. Balucani

T_6

Workshop Opening
Paolo Nenzi and Wladek Grabinski
Workshops Organizing Committee

T_7

Impact of Statistical Parameter Set Selection on Accuracy of Statistical Compact Modelling
B. Cheng, N. Moezi, D. Dideban, C. Millar, S. Roy, A. Asenov
University of Glasgow

T_8

Compact Modeling for Process Variability and Aging Effects
Ehrenfried Seebacher
austriamicrosystems

T_9

Positioning S-Parameters, Harmonic Measurements and X-Parameters for Device Modeling
Franz Sischka
Agilent Technologies, Germany

10:40-11:00

Coffee Break

T_10

Deterministic Solution of the 1D Boltzmann Transport Equation: application to the study of current transport in nanowire FET
G. Baccarani, E. Gnani, A. Gnudi, S. Reggiani
ARCES, University of Bologna

T_11

Extraction of a Scalable Electrical Model for a SOI JFET
Simona Cozzi, Lorenzo Labate, and Roberto Stella
STMicroelectronics, Cornaredo, Italy

T_12

A physics-based model for Charge-Trapping memory simulation
Andrea Padovani and Luca Larcher
DISMI, Università di Modena e Reggio Emilia

12:00-13:00

Poster Session - Chair: W. Grabinski

Lunch

14:30

April 9 - Afternoon Session - Chair: P.Nenzi

T_13

Multi-gate non-volatile memories under uniform stress operation: electrical characteristics & physical modeling
L. Perniola
CEA-LETI MINATEC

Abstract:
In this work we present the electrical behaviour of trigate SONOS FinFet (FF) and of SONOS Gate-All-Around (GAA) and compare it to standard SONOS planar cells. In particular performances under Fowler-Nordheim stress are analysed in order to extrapolate operation in standard NAND architectures. The essential features of such complex 3D device architectures can be explained with simple 1D models that capture the electric field E and coupling factor ?G boost due to the rounded active surface (ie nanowire channel in the case of GAA and corners in the case of FF). Electric field along the SONOS gate stack can be described in axial coordinates, so naturally electric field peaks at channel-tunnel oxide interface. Thanks to such a simple approach the following features can be quantitatively explained for GAA: Program enhancement when reducing the radius of nanowire in GAA; Erase operation is possible even with 6-nm thick tunnel oxide in GAA (normally prohibitive in planar devices) and erase speed is higher in GAA than in planar devices with even thinner tunnel oxide; typical erase saturation effect present in planar cells is avoided in GAA; Retention performance is better in GAA with respect to planar cells. As a conclusion, thanks to corner effect, tunnel oxide barrier in GAA plays the role of a crested barrier: it allows a faster write/erase while keeping very good sealing properties in retention conditions. Concerning FF, fin corners and fin side/top are modelled through a parallel composition of two floating gate memories described in axial (for corners) and planar (for fin side/top) fashion. In particular SOI as well as Body-Tied (BT) device architectures can be modelled solving the electrostatics of SOI and BT in a compact form through the Green’s functions. The following electrical features can be explained for FF: Program enhancement when reducing fin width can only be explained through non-uniform distribution of trapped charge along fin corners and fin top/side, as uniform trapped charge distribution around fin would imply a programming window ?VTH shrink, reducing fin width; Retention performance can be explained by charge loss at fin corners; Gate Disturb suffers of the interplay between different tunnelling dynamics along fin corners and fin top/side, and eventually a non-monotonic device electrical behaviour is observed. Concerning scaling performances, the physical modelling will be used to extrapolate information to the most aggressive pitch dimensions. It will be shown that starting from BT-trigate, with 1:1 aspect ratio between fin top/fin side, VTH enlarges, reducing fin side and fin width features; while starting from an SOI-trigate, VTH benefits much more of a fin side than fin width reduction. Moreover for GAA, it will be shown that reducing the nanowire diameter helps in boosting the VTH dynamics, even if VTH at saturation lowers for the smallest nanowires.

T_14

Modeling of Seasoning Effects in Phase Change Memory Arrays
Cristian Zambelli and Andrea Chimenton and Piero Olivo
University of Ferrara

T_15

Convergence Aid Techniques for Compact Modeling with Verilog-A
S. Mijalkovich and B. Floyd
Silvaco Europe Simucad Design Automation

T_16

Development of an Enhanced ADS® Electrothermal Simulation Tool for RF Circuits
Salvatore Russo, Vincenzo d'Alessandro, Niccolò Rinaldi
University of Naples Federico II

16:00

Workshp Closing

Committee:

Fernanda Irrera, Uni Roma; Technical Program Chair
Fabrizio Famà, Micron Technology Italia; Technical Program Co-Chair
Marco Balucani, Uni Roma; Technical Program Co-Chair
Paolo Nenzi, Uni Roma; Organization Coordinator
Extended MOS-AK/GSA Committee:
Lisa Tafoya, Vice President, Global Semiconductor Alliance (GSA)
Chelsea Boone GSA; Senior Research Analyst
Wladek Grabinski, GMC Suisse; MOS-AK/GSA Group Manager
MOS-AK/GSA North America:
Chair: Pekka Ojala, Exar Corporation
Co-Chair: Geoffrey Coram, Analog Devices
Co-Chair: Prof. Jamal Deen, U.McMaster
MOS-AK/GSA South America:
Chair: Prof. Gilson I Wirth; UFRGS; Brazil
Co-Chair: Prof. Carlos Galup-Montoro, UFSC; Brazil
MOS-AK/GSA Europe:
Chair: Ehrenfried Seebacher, austriamicrosystems AG
Co-Chair: Sebastian Schmidt, XFab
Co-Chair: Prof. Benjamin Iniguez, URV
MOS-AK/GSA Asia/Pacific:
Chair: Goichi Yokomizo, STARC, Japan
Co-Chair: Sadayuki Yoshitomi, Toshiba, Japan
Co-Chair: Xing Zhou, NTU, Singapore

No.#30012

update: MAR. 2010 (rev.e)