Arbeitskreis MOS-Modelle und Parameterextraktion
MOS Modeling and Parameter Extraction Working Group
MOS-AK/GSA ESSDERC/ESSCIRC Workshop
Sept.17, 2010  Seville
MOS-AK 2010: over Two Decades of Enabling Compact Modeling R&D Exchange
 Technical MOS-AK/GSA Program Promoters
IEEE EDS
EuroTraining MOSIS
The MOSIS Services
GSA 
COMON EC Project
Preannouncement 
Register: Free on-line registration will be available after 2nd announcement
Venue: Barceló Renacimiento Hotel Seville
Agenda:
  • Sept. 17, 2010
    • MOS-AK/GSA ESSDERC/ESSCIRC Workshop
Important Dates:
  • 1st Announcement - April 2009
  • Call for Papers - May 2009
  • 2nd Announcement - June. 2010
  • Final Workshop Program - Aug. 2010
  • MOS-AK/GSA Workshop - Sept.17, 2010
Synopsis:
  • HiTech forum to discuss the frontiers of electron device modeling with emphasis on simulation-aware models.
  • MOS-AK/GSA Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/Spice modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme - frontiers of the compact modeling for nm-scale MEMS designs and CMOS/SOI circuit simulation.
  • The specific workshop goal will be to classify the most important directions for the future development of the electron device models, not limiting the discussion to compact models, but including physical, analytical and numerical models, to clearly identify areas that need further research and possible contact points between the different modeling domains. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe) who are interested in device modeling; ICs designers (RF/Analog/Mixed-Signal/SoC) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind the IC simulation in modern device models.
Topics: to be covered include the following:
  • Compact Modeling (CM) of the electron devices
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • CM of passive, active, sensors and actuators
  • Emerging Devices, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and IC Designs
  • Foundry/Fabless Interface Strategies
On-line abstract submission will be open after 1st announcement.
Committee: Extended MOS-AK/GSA Committee:
  • Lisa Tafoya, Vice President, Global Semiconductor Alliance (GSA)
  • Chelsea Boone GSA; Senior Research Analyst
  • Wladek Grabinski, GMC Suisse; MOS-AK/GSA Group Manager
    MOS-AK/GSA North America:
  • Chair: Pekka Ojala, Exar Corporation
  • Co-Chair: Geoffrey Coram, Analog Devices
  • Co-Chair: Prof. Jamal Deen, U.McMaster
    MOS-AK/GSA South America:
  • Chair: Prof. Gilson I Wirth; UFRGS; Brazil
  • Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil
    MOS-AK/GSA Europe:
  • Chair: Ehrenfried Seebacher, austriamicrosystems AG
  • Co-Chair: Sebastian Schmidt, XFab
  • Co-Chair: Prof. Benjamin Iniguez, URV
    MOS-AK/GSA Asia/Pacific:
  • Chair: Goichi Yokomizo, STARC, Japan
  • Co-Chair: Sadayuki Yoshitomi, Toshiba, Japan
  • Co-Chair: Xing Zhou, NTU, Singapore
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update: FEB 2010 (rev. A)
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