Cadence Design Systems
2655 Seely Ave
San Jose, CA 95134
Building 5 (map)

Abstract: 
Use of Artificial Intelligence methods in general, and the application of specific optimization techniques, neural networks, and learning algorithms to semiconductor parametric test and model generation is described. In Parametric Test arena the goal is to improve the quantity and quality of the data by accelerating testing speed and breaking conventional test hardware constraints. Revolutionary “behavior-aware” testing methods implemented at the instrument level, DUT level and production test level are outlined. Use of learning algorithms to automate model generation is also outlined. The paper presents key concepts and summarizes some specific results.

Abstract: 
Scaled transistor technologies encounter additional reliability challenges besides bias temperature instability, time dependent dielectric breakdown and hot carrier degradation. Time-zero variability and variability induced by device aging is a growing concern which needs to be modeled using stochastic processes. The physical nature of the stochastic process remains under debate and to support model development efforts large statistical data sets are essential. In addition, self-heating during reliability testing can be observed in novel device structures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices and needs proper attention. Apart from model development for the individual reliability mechanisms, variability and self-heating, it is critical to provide a platform integrating their impact for a circuit level assessment. In this presentation we discuss how to obtain stochastic BTI data for discrete SRAM and logic device beyond 3s, address silicon validated modeling of degradation in RO/SRAM plus explore self-heating effects in FinFET and SOI devices.