Arbeitskreis MOS-Modelle und Parameterextraktion
MOS Modeling and Parameter Extraction Group
MOS-AK Meeting
organizers: Fabien Prégaldiny, Christophe Lallement and Wladek Grabinski
in cooperation with Institut d'Electronique du Solide et des Systèmes and Ansoft
8 April 2005, Strasbourg 

Organizers:

Sponsors:
ENSPS
INESS
Freescale
ANSOFT
  Final Program
 9:25 - 9:30 W.Grabinski
Introduction
 9:30-11:00
Morning Session
Chairmen: 
Fabien Prégaldiny and Wladek Grabinski

Daniel Mathiot (InESS):
Welcome address and research activities at InESS

Patrick Martin, Mickaël Boasis, Olivier Rozeau, Jérôme Prouvee and David Axelrad (LETI/CEA-Grenoble):
Wafer-Level Extraction of BSIMSOI Low Frequency Noise Parameters for 130 nm Partially-Depleted SOI MOSFETs


Luc Hebrard, J.-B. Kammerer, M. Hehn, V. Frick, A. Schuhl, P. Alnot, P. French and F. Braun (InESS):
CMOS compatible integrated magnetometers

Jean-Claude Perraud (ENSI CAEN):
New Verilog A compiler for SPICE 3F5

Coffee Break
11:15-12:00
Poster Session
Chairmen: Jean-Michel Sallese and
Wladek Grabinski

D. Jiménez, B. Iñíguez, J. Roig, J. Suñé, L. F. Marsal, J. Pallarès and D. Floresc (U.Barcelona):
Analytical continuous I-V model of the Surrounding-Gate MOSFET

Jean-Baptiste Kammerer, L. Hebrard and F. Braun (InESS)
Implementation of an hysteresis model in VHDL-AMS for compact modeling of spintronics devices

Larry Dangremond (Cascade):
Eliminating radio frequency interference effects on 1/f, Vt, gm and capacitance measurements

Alain MICHEL (Ansoft Europe):
Nexxim®:  Ansoft’s New State-of-the-Art Circuit Simulator for RF, Analog and Mixed-Signal Design

Fadhila Haned, M. Ben Chouikha, G.Alquié (LISIF, Pierre et Marie Curie University, Paris):
An Improved BDJ Color Detector Physical Model


M. Alwan, B. Beydoun, K. Ketata, M. Zoaeter (Rouen University IUT-LEMI)
2D analysis of a power VDMOS transistor CV characteristics temperature effects
12:00-13:30
Lunch
13:30-16:30
Afternoon Session
Chairmen:
Christophe Lallement and Wladek Grabinski

Franz Sischka (Agilent):
EM substrate effects modeling using Agilent Momentum

Birahim Diagne, Fabien Prégaldiny, François Krummenacher, François Pécheux, Jean-Michel Sallese and Christophe Lallement (InESS/EPFL/LIP6)
Design Oriented Model for Symmetrical DG MOSFET

Thomas Zimmer (IXL Bordeaux):
Self-heating investigation of bulk and SOI transistors

D. Rideau, F. Gilibert and M. Minondo (STM):
Modelling Strained Silicon Devices

Johannes Fellner (austriamicrosystems AG):
A CMOS compatible PolyFuse element used in a One Time Programmable circuit


16:30
End of the MOS-AK Workshop

Publication Partner:
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
Editor, Europe: Phil Mawby
IJNM_Wiley
Abstracts

Daniel Mathiot (InESS):
Welcome address and research activities at InESS
InESS (Institut d'Electronique du Solide et des Systèmes : Institute for solid state electronics and electronics of systems) is a new laboratory resulting from the association of two former laboratories, PHASE (Physics and Applications of Semiconductors) and LEPSI (Laboratory of Electronics and Physics of Integrated Systems). The new laboratory is a "mixed research unit" of the Louis Pasteur University (Strasbourg) and CNRS (French National Research Center). The research activities of InESS span various topics, extending from solid state electronics to electronics of systems. The different themes are thus concerned with materials and nanotechnologies for electronic devices, materials and concepts for photovoltaics, optoelectronic instrumental systems and microsystems, and integrated instrumental systems.


Patrick Martin, Mickaël Boasis, Olivier Rozeau, Jérôme ProuvÉe and David Axelrad (LETI/CEA-Grenoble):
Wafer-Level Extraction of BSIMSOI Low Frequency Noise Parameters for 130 nm Partially-Depleted SOI MOSFETs
Accurate modeling of low frequency noise has become essential for downscaled analogue and RF circuits design, because low frequency noise is upconverted to high frequencies through the phase noise. Point-probe noise measurements enable the extraction of BSIMSOI noise parameters (EF, NOIA, NOIB, NOIC and NOIF) referring to physical  µ- N flicker noise model based on mobility correlation. Indeed, theoretical  µ- N model is implemented in BSIM code thanks to relationships linking the oxide trap density Nt and the Coulomb scattering coefficient   to their equivalents in circuit simulators. Nevertheless, measurements carried out on 130 nm PD SOI MOSFETs suggest the need for a 103 factor in the equivalence relationships according to the BSIMSOI version.


Luc Hebrard, J.-B. Kammerer, M. Hehn, V. Frick, A. Schuhl, P. Alnot, P. French and F. Braun (InESS):
CMOS compatible integrated magnetometers
The main physical principles for magnetic sensing leading to magnetometers which can be integrated into a silicon die are reviewed . Then 1D, 2D and 3D integrated Hall effect magnetic sensors in CMOS technologies are discussed with their potential applications. These magnetometers are still integrated with a surrounding electronics and the need for accurate compact models is emphasized. In a second part, we present a 2D magnetic sensor based on a Magnetic Tunnel Junction (MTJ). This new magnetometer is a good candidate for integration into CMOS thru simple post-processing. This sensor relies as much on the MTJ device as on its associated electronic system. Here again, in order to simulate the whole magnetometer, the need for a good compact model of the MTJ is emphasized.


Jean-Claude Perraud (ENSI CAEN):
New Verilog A compiler for SPICE 3F5
From a Verilog A source model, it generates all the C files that allows to manually install the new model into Spice3F5,or using a new Spice command,load directly the new compiled model into spice (using shared-lib mechanism). It has mainly all the features of Verilog A needed for model generation, and some new extensions to simplify the Verilog A sources: Verilog A Analog function with InOut parameters, No return Value Analog function, you may define separately device and model parameters, Macros may have more than 1 lines. It has been already validated for the following Spice analysis: OP, DC, AC, TRAN, PZ, and related analysis. Noise analysis interface in development. Also in development a new SPICE3F5 extension with RF HARMONIQUE BALANCE,that includes S parameter Analysis,Port,Nport,HB analysis(steady-state/1 forced source), QP analysis (steady-state/2 forced sources),CE analysis (TRAN HARMONIQUE BALANCE 2 forced sources). Already, the New VERILOG A Model Compiler generates also the C files for the RF HARMONIQUE BALANCE analysis.


D. Jiménez, B. Iñíguez, J. Roig, J. Suñé, L. F. Marsal, J. Pallarès and D. Floresc (U.Barcelona):
Analytical continuous I-V model of the Surrounding-Gate MOSFET
A continuous analytic current–voltage (I–V) model for cylindrical undoped (lightly doped) surrounding gate (SGT) MOSFETs is described. It is based on the exact solution of the Poisson’s equation, and the current continuity equation without the charge-sheet approximation, allowing the inversion charge distribution in the silicon film to be adequately described. This model correctly traces the transition between the different operation regions without resorting to fitting parameters, being ideal for the kernel of SGT MOSFETs compact models. We demonstrate that the I–V characteristics obtained by this model agree with three-dimensional numerical simulations for all ranges of gate and drain voltages.


Jean-Baptiste Kammerer, L. Hebrard and F. Braun (InESS)
Implementation of an hysteresis model in VHDL-AMS for compact modeling of spintronics devices
Spintronics devices such as magnetic tunnel junctions or giant magnetoresistances have been recently integrated to standard CMOS processes. This kind of devices can be used to design random access memories, transistors or magnetic sensors. Nevertheless, the electrical properties of spintronics devices depend on the magnetization of their ferromagnetic layers and accurate hysteresis models are needed for compact modeling of such devices. Here, such an hysteresis model written in VHDL-AMS is described and a simple magnetic tunnel junction compact model based on this hysteresis model is presented. Simulation results of a MRAM cell and of magnetic sensors are also shown.


Larry Dangremond (Cascade):
Eliminating radio frequency interference effects on 1/f, Vt, gm and capacitance measurements
Some measured parameters are highly susceptible to spurious electrical noise that impinges on a wafer device. Example affected measurements are Vth & Id, gm, several capacitance parameters, and of course flicker noise. The offenders may be radiated or conducted emissions from external sources or locally generated emissions. Improvements in isolation, shielding, power supplies, and filters of on-wafer systems have been recently initiated that enhance measurement accuracy , ease and speed . This presentation shows examples of affected data and improved results.


Alain MICHEL (Technical Director, Ansoft Europe):
Nexxim®: Ansoft’s New State-of-the-Art Circuit Simulator for RF, Analog and Mixed-Signal Design
Nexxim® is Ansoft’s new circuit simulator that provides fast and accurate solutions for tough analog and mixed-signal circuits. It provides the transistor-level simulation accuracy required for sensitive analog and wireless front-end circuits and the capacity to solve the complexities in modern mixed-signal integrated circuits. Transient and harmonic balance simulations can be performed from a single netlist using the same time-domain device models for broad simulation and analysis of analog and RF circuits. New numerical algorithms and advanced software engineering combine to deliver orders of magnitude improvement in simulation speed, accuracy, and capacity compared to other commercial simulators. Full compatibility to HSPICE® netlist format provides full foundry device model support and allows Nexxim to integrate into most EDA flows. Dynamic links to the HFSS® electromagnetic field solver provides on-chip passive and IC package modeling. Integration within the Ansoft Designer® environment provides schematic capture, netlist generation and editing, simulation, dynamic links to system and planar EM simulation, and results post processing. This presentation introduces Nexxim’s capabilities and advantages and describes its use within the general design flow of RF/Mixed-signal IC design.


Fadhila Haned, M. Ben Chouikha, G.Alquié (LISIF, Pierre et Marie Curie University, Paris):
An Improved BDJ Color Detector Physical Model
The BDJ (Buried Double pn Junction) color detector structure in a standard n-well CMOS technology consists of two buried pn junctions. By using the optical properties of silicon, each active area gives the color information without use of optical filters The BDJ photocurrents spectral responses present two peaks in the wavelength range 400 to 800 nm and the photocurrents ratio shows a monotonically increasing function with the wavelength. Thus, both wavelength and optical power of a monochromatic light can be determined. This allows the use of the BDJ device for accurate multispectral cameras and in imaging systems development. However, successful design of color sensor using this detector requires an accurate knowledge of it behavior. The physical model of the BDJ photocurrents has been proposed in previous works. Even if simulation results seem to give good fit to experimental data, the difference between measurements and simulations remains important. In order to develop a reliable model that simulates accurately the BDJ behavior, we adopted a new modeling approach. The approach consists on experimental extraction of most physical and electrical parameters. It takes also into account the physical phenomena that intervene to form the BDJ dark and photo-generated currents. Simulation results of both dark and photo-generate currents are compared to measurements curried out on a test chip designed and manufactured using a standard CMOS process. To evaluate our model accuracy, we calculated at every wavelength the relative error between simulation results and measurements. We note that by using our modeling approach the difference is reduced. It is about 1% in the wavelength range 490 to 750 nm.


M. Alwan, B. Beydoun, K. Ketata, M. Zoaeter (Rouen University IUT-LEMI)
2D analysis of a power VDMOS transistor CV characteristics temperature effects
TBD


Franz Sischka (Agilent):
EM substrate effects modeling using Agilent Momentum


Birahim Diagne, Fabien Prégaldiny, François Krummenacher, François Pécheux, Jean-Michel Sallese and Christophe Lallement (InESS/EPFL/LIP6)
Design Oriented Model for Symmetrical DG MOSFET
A new charge-based compact model for undoped DG MOSFET under symmetrical operation is presented. This design oriented model gives insight into the physical phenomena and is especially dedicated to the circuit designer. Based on the EKV formalism, useful normalizations are proposed and successfully implemented in the model. This allows to greatly simplify the model formulation in deriving current and charges in a very comprehensive form. In order to validate the analytical model, we have also developed the 2D simulations of a DG MOSFET structure (tox=2nm, tsi=25nm) and performed both static and dynamic electrical simulations of the device. Comparisons with the 2D numerical simulations give evidence for the good behavior and the accuracy of the model. In particular, the ideal sub-threshold slope (60mV/decade) that takes place in the weak-inversion region (also called the "volume inversion region" for the DG MOSFET) is well described. Finally, the VHDL-AMS implementation of the DG MOSFET model is carried out leading to fast and efficient simulations.


Thomas Zimmer (IXL Bordeaux):
Self-heating investigation of bulk and SOI transistors
This presentation deals with the self-heating effect in bulk and SOI transistors. The static and dynamic self-heating mechanism is investigated. The resulting theoretical model is implemented in an electrical equivalent circuit. The approach is validated through measurements on devices from different technologies. System configuration, measurement, and calibration issues are presented.


D. Rideau, F. Gilibert and M. Minondo (STM):
Modelling Strained Silicon Devices
Modelling the mechanical stress-induced effects on MOSFETs capacitance and currents becomes a crucial issue for device simulation. From the one hand, the scaling down of MOSFETs gives rise to parasitic mechanical stress such as sidewell oxidation volume expansioninduced stress. One the other hand, strained Si is becoming an essential component in device application due to its enhanced carrier mobility. Strained Si on relaxed SiGe buffer layer or film-induced stress are typical techniques used to improve device performance. Based on numerical simulations of the electronic band structure, we review the impact of the stress on the first order MOSFETs parameters. We also show that some basic parameters such as the effective mass or the band gap are strongly stress-dependant.


Johannes Fellner (austriamicrosystems AG):
A CMOS compatible PolyFuse element used in a One Time Programmable circuit
A Poly Fuse element, which is based on a 2-layer approach, was developed to be used as an 'One Time Programmable' element in a 0.35um standard CMOS process. Optimal programming conditions are defined as well as drifts of the programming conditions and their impact on the Poly fuse reliability are monitored. TEM/SEM analysis gives corresponding physical explanations for the electrical effects seen for different programming conditions. For process control the Poly Fuse and the corresponding programming transistor is implemented into the standard Scribe Line Monitor. So it is possible to get the variation of unprogammed and programmed values for statistics. The implementation of the Poly Fuse into a circuit takes care of all reliability restrictions and is focussed on a high programming yield. Due to the requirement of larger numbers of bits, the OTP structure is combined with a RAM structure to share the control logic. A state machine handles the interaction and has implemented also a startup sequence. After startup, the block has a RAM compatible access to the data. Some defined bits can be used directly for trimming purpose.

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