Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
12th MOS-AK ESSDERC/ESSCIRC Workshop
September 26, 2014
Venice
MOS-AK: Over Two Decades of Enabling Compact Modeling R&D Exchange
MOS-AK Workshop Sponsors
Coventor
LFoundry
Tanner EDA

MDC Europe
MOSIS
The MOSIS Services

Technical MOS-AK Program Promoters
Eurotraining
EDA Solutions
IJHSES
Publishing Partner
Final MOS-AK Workshop Program
Venue:
Palazzo del Casinò
Lungomare Marconi, 30
30126 Venice Lido, Italy
Agenda
Display Format: Citation Citation & Abstract
08:30-08:50 On-site Registration
08:50-12:30 Morning Session: Open Source CAD/EDA Tools for Compact Modeling
T_1
Parallel Circuit Simulation: How Good Can It Get?
Andrei Vladimirescu
ISEP (FR); UCB (USA)
T_2
CUSPICE: The revolutionary NGSPICE on CUDA Platforms
Francesco Lannutti
Sapienza University of Rome (I)
T_3
Circuit Simulation Update: GPU Progress; Electrothermal Cosimulation
Rick Poore
Keysight Technologies (USA)
10:30-11:00
Coffee break
T_4
QUCS Roadmap:
background to the new features in release 0.0.18 and an outline of future software development directions
Mike Brinson, Richard Crozier, Clemens Novak, Bastien Roucaries, Frans Schreuder, Guilherme Brondani Torri
QUCS Development (EU)
T_5
Comparative Analysis of SOI/SOS MOSFET SPICE Models with Account for Radiation Effects
Konstantin Petrosyants(1), Igor Kharitonov (1), Lev Sambursky (1,2)
(1) MIEM HSE (RU), (2) IPPM RAS (RU)
P_1
Flicker Noise Modeling in BSIM6 Compact Model
Harshit Agarwal and Yogesh Singh Chauhan
IIT Kanpur (IN)
12:30-13:30
Lunch
13:30-16:30
Afternoon MOS-AK Session: Device Level SPICE/Verilog-A Modeling
T_6 
Total Virtual Fabrication of Advanced CMOS Devices and Processing
W. Clark, M. Hargrove, G. Schropfer, D. Fried
Coventor (F)
T_7 
Performance Comparison of Hall Effect Sensors Obtained by Regular Bulk or SOI CMOS Technology
Maria-Alexandra Paun
University of Cambridge, (UK)
T_8 
RF Characterization and Modeling of Nanoscale MOSFET from Weak to Strong Inversion
Maria-Anna Chalkiadaki and Christian Enz
EPFL STI IMT ICLAB (CH)
T_9 
Compact Model of Tunneling Field Effect Transistor for Ultra-low Voltage Circuit Analysis
Chika Tanaka, Kanna Adachi, Motohiko Fujimatsu, Akira Hokazono, Yoshiyuki Kondo, Daisuke Matsushita, and Shigeru Kawanaka
Toshiba Corporation (J)
T_10 Compact Modeling of Junctionless Cylindrical Nanowires
Benjamin Iniguez, Oana Moldovan and François Lime
URV, Tarragona (SP)
16:30
End of the MOS-AK Workshop
16:30-17:30
IEEE WIE Affinity Group Meeting

Dr. Maria-Alexandra Paun, Chair of IEEE Switzerland WIE (Women in Engineering) Affinity Group, will briefly present the activities of IEEE WIE - All attendees are welcome to this discussion.
   As an IEEE Affinity Group we aim at promoting and recognizing the merits of women scientists. We also strive to encourage the careers of young female engineers, by providing them with role models from the scientific and research environment, and their exemplary achievements. At more practical level, we organize discussions and meetings, various competitions, etc.

Extended MOS-AK/GSA Committee:
Committee
  • Technical Committee
    MOS-AK/GSA North America
  • Chair: Pekka Ojala, Exar Corporation
  • Co-Chair: Geoffrey Coram, Analog Devices
  • Co-Chair: Prof. Jamal Deen, U.McMaster
  • Co-Chair: Roberto Tinti, Agilent EEsof Division
    MOS-AK/GSA South America
  • Chair: Prof. Gilson I Wirth; UFRGS; Brazil
  • Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil
  • Co-Chair: Sergio Bampi, UFRGS, Brazil
  • Co-Chair: Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
    MOS-AK/GSA Europe
  • Chair: Ehrenfried Seebacher, AMS, Austria
  • Co-Chair: Alexander Petr, XFab, Germany
  • Co-Chair: Prof. Benjamin Iniguez, URV, Spain
  • Co-Chair: Franz Sischka, SisCon, Germany
    MOS-AK/GSA Asia/South Pacific

  • Chair: Sadayuki Yoshitomi, Toshiba
  • Co-Chair: Xing Zhou, NTU Singapore   
  • Co-Chair: A.B. Bhattacharyya, JIIT New Delhi
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No.#3199
update: Oct 2014 (rev.f)
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