| Important
Dates: |
- Call for Papers - Dec.
2019
- 2nd Announcement - Feb. 2020
- Final Workshop Program - May 2020
- MOS-AK Workshop:
July 8: SiC training course by Fraunhofer IISB
July 9-10: MOS-AK Workshop
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|
Paper |
Submission deadline: April 2019
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Venue:
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Xidian University xidian.edu.cn |
| Online |
Registration
to be open in April 2020
any
related enquiries can be sent to registration@mos-ak.org |
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Synopsis and Workshop Topics
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| Synopsis: |
- HiTech forum to discuss
the frontiers of electron device modeling with emphasis on
simulation-aware compact/SPICE models and its Verilog-A standardization.
- MOS-AK
Meetings are organized with aims to strengthen a network and discussion
forum among experts in the field, enhance open platform for information
exchange related to compact/Spice modeling and Verilog-A
standardization,
bring people in the compact modeling field together, as well as obtain
feedback from technology developers, circuit designers, and CAD tool
vendors. The topics cover all important aspects of compact model
development, implementation, deployment and standardization within the
main theme - frontiers of the compact modeling for nm-scale MEMS/NEMS
designs, CMOS/SOI and HEMT IC simulation.
- The
specific workshop goal will be to classify the most important
directions for the future development of the electron device models,
not limiting the discussion to compact models, but including physical,
analytical and numerical models, to clearly identify areas that need
further research and possible contact points between the different
modeling domains.
This workshop is designed for device process engineers (CMOS, SOI,
BiCMOS, SiGe, GaN, InP) who are interested in device modeling; ICs
designers
(RF/Analog/Mixed-Signal/SoC/Bio/Med) and those starting in that area as
well as
device characterization, modeling and parameter extraction engineers.
The content will be beneficial for anyone who needs to learn what is
really behind the IC simulation in modern device models.
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| Topics: |
to be covered include the
following:
- Advances in
semiconductor technologies and
processing
- Compact Modeling (CM) of
the electron devices
- Verilog-A language for
CM standardization
- New CM techniques and
extraction software
- Open Source FOSS
TCAD/EDA modeling and
simulation
- CM of passive, active,
sensors and actuators
- Emerging Devices, CMOS
and SOI-based memory cells
- Microwave, mmW, RF
device
modeling, high voltage device modeling
- Microsystems, SoC, IP
modeling
- Device level modeling
for Bio/Med applications
- Nanoscale semiconductor
devices/circuits
and its reliability/ageing
- Technology R&D,
DFY, DFT and IC Designs
- Foundry/Fabless
Interface Strategies
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|
International
MOS-AK
Committee: |
| Committee |
- International MOS-AK Board of R&D Advisers
- Larry Nagel, Omega Enterprises
Consulting (USA)
- Andrei Vladimirescu, UCB
(USA); ISEP (FR)
- MOS-AK
Technical Committee
MOS-AK
North
America
- Chair: Pekka Ojala, Exar Corporation (USA)
- Co-Chair: Geoffrey Coram, Analog Devices (USA)
- Co-Chair: Prof.
Jamal Deen,
U.McMaster (CA)
- Co-Chair: Roberto
Tinti, Keysight EEsof Division (USA)
MOS-AK
South
America
- Chair: Prof. Gilson I Wirth; UFRGS (BR)
- Co-Chair: Prof. Carlos Galup-Montoro, UFSC (BR)
- Co-Chair: Sergio
Bampi, UFRGS (BR)
- Co-Chair: Antonio
Cerdeira Altuzarra, Cinvestav - IPN (MX)
- Co-Chair: Roberto
S. Murphy, INAOE (MX)
- MOS-AK
Europe
- Chair: Ehrenfried Seebacher, AMS (A)
- Co-Chair: Suba
Subramaniam,
XFab (D)
- Co-Chair: Prof.
Benjamin Iniguez,
URV (SP)
- Co-Chair: Franz Sischka, SisConsult, (D)
MOS-AK
Asia/South Pacific
- Chair: Sadayuki
Yoshitomi, Toshiba
(J)
- Co-Chair: A.B.
Bhattacharyya, JIIT
New Delhi (IN)
- Co-Chair: Min Zhang, XMOD Tech, Shanghai (CN)
- Co-Chair: Kaikai
Xu, 电子科技大学 (CN)
- Co-Chair: Xing
Zhou, NTU
Singapore (SG)
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