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Agenda: Sept. 18 2009 in Athens
Morning Session 9:00-11:30 Oral presentations 10:00-10:30 (coffee break)	Poster Session 11:30-12:00 Posters 12:00-13:00 (lunch)	Afternoon Session 13:00-16:00 Oral presentations 14:30-15:00 (coffee break)

"Frontiers of Compact Modeling" Workshop Program

Display Format: Citation Citation & Abstract
Register	Free on-line registration
Venue	DIVANI CARAVEL HOTEL, 2 Meg. Alexandrou Aven. 161 21, Athens, Greece For driving directions please visit: www.ametro.gr and www.oasa.gr
9:00-11:30	Morning Session - Chair: Matthias Bucher, TUC
P_1	SPICE and Models - Perfect Together Laurence Nagel* and Colin McAndrew** *Omega Enterprises Consulting; **Freescale Semiconductor Abstract:  From the very beginning of the integrated circuit industry, the design of integrated circuits has required an accurate analog simulator. Engineers entering the electronics industry today weren’t even born when the first version of SPICE was released by the University of California, Berkeley, in 1971. As the fabrication technology for integrated circuits has improved, SPICE and other analog simulators have evolved to accommodate larger, more complex circuits, to provide a richer suite of analysis capabilities, and to support an increasingly diverse set of semiconductor device models. Throughout this evolution, SPICE and the device models included within it have always had a symbiotic relationship: the best simulation algorithms available combined with lousy models will create erroneous simulation results, and the most accurate device models available combined with a lousy simulator will yield no answers at all. There also has been a very symbiotic relationship between engineers who develop the simulators and engineers who develop the device models. This paper describes the co-evolution of analog simulators and device models from the viewpoints of two engineers, one a simulator developer and one a device modeler, who have worked together for a long time and yet are still the best of friends.
P_2	CMOS Statistical Variability for Compact Modeling Asen Asenov Uni. Glasgow Abstract:  Statistical variability, arising from the discreteness of charge and matter, poses increasing challenges to CMOS scaling and integration, and demands the introduction of statistical circuit and system design strategies and verification. Compact Models (CM) are the interface between technology and design and the statistical device variability that affects the circuit/system performance and yield must be accurately represented by the industry standard CM. Historically the focus of CM was the accurate representation of individual device characteristics instead of the statistical behaviour of ensembles of microscopically different transistors. As a result, the current industry standard compact models do not have the natural structures and parameters to incorporate the truly SV associated with Random Discrete Dopants (RDD), Line Edge Roughness (LER), Poly Gate Granularity (PGG) and other dominant statistical variability sources. On the other hand, in order to achieve reasonable performance and yield in contemporary CMOS design, the designers should have the ability to carry out variability aware statistical design using the currently available compact models. In this talk based on comprehensive statistical 3D simulation results of contemporary MOSFETs we compare different statistical CM parameter identification strategies for BSIM4 and PSP, providing critical information regarding their accuracy.
P_3	Leakage- and Variability-Conscious Circuit Designs for the 0.5-V Nanoscale CMOS Era Kiyoo Itoh Hitachi Ltd. Abstract:  Reviews and perspectives of low-voltage circuits for nanoscale memory-rich CMOS LSIs are described, mainly focusing on leakage and variability of MOSFETs. In the first half of the talk, state-of-the-art low-voltage circuits are reviewed in terms of reducing the minimum operating voltage Vmin. Here, Vmins of logic, SRAM, and DRAM blocks are compared, revealing that the SRAM block is problematic most because of the highest Vmin of the three. SRAM cells, exemplified by 6- and 8-transistor cells, are then reviewed with respect to Vmin and cell size. In the second half of the talk, perspectives for the 0.5-V nanoscale CMOS era are presented, citing some breakthrough technologies. After clarifying impact of advanced MOSFETs (e.g. high-k metal-gate MOSFETs and FinFET) on reducing Vmins, dual-VDD dual-Vt dynamic circuits for further reducing Vmins are discussed. For ensuring the resultant reduced Vmin with reduced power supply noise, a differentially-driven power switch suitable for many-core LSIs, and tiny logic-compatible FinFET DRAM cell for reducing the core or chip size that has been dominated by an SRAM array are also described. Following that, a scenario to the 0.5-V nanoscale CMOS era is presented.
P_4	Structured Analog CMOS Design Danica Stefanovic Marvell Abstract:  Standard analog design procedure is usually based on a large number of simulations, strongly depends on the type of analog circuit that has to be implemented and requires a lot of manipulation at the transistor level. Simulators offer accurate modeling and precise calculations, but on the other hand ascertaining circuit parameter dependences is difficult and depends on analog designer expðÔ�ÝçUðÔ�ÝçU ¸zÝçUÀ¯|ÝçUXÕ�ÝçUÕ�ÝçU$/Õ�ÝçU increases, since the design specifications become more severe in terms of gain and speed, requiring at the same time minimization of the circuit surface. Structured analog design approach makes it possible to simplify complex analog design problems and develop a global design strategy that can be used for the design of different analog cells. The basic concept consists in analog cell partitioning into the basic analog structures and sizing of these basic analog structures in a predefined procedural design sequence. The basic analog structure specifications are derived from circuit-level requirements, and its sizing in the environment imposed by the circuit demands less effort. The proposed transistor-level design is based on the continuous MOS modeling approach and relies on the device inversion level as a fundamental design variable. Furthermore, several procedural design scenarios are implemented as a CAD tool that guides and assists the user during analog design tasks and provides an interactive interface that allows instantaneous visualization of design trade-offs.
11:30-12:00	Poster Session - Chair: Wladek Grabinski, GMC Suisse
12:00-13:00	Lunch break
13:00-16:00	Afternoon Session - Chair: Benjamin Iniguez, URV
P_5	Rapid On-Chip Electromagnetic Extraction and Compact Modeling with Guaranteed Passivity Sotiris Bantas Helic S.A. Abstract:  We have proposed a tool for lumped element modeling of on-chip passives and interconnects as a contender to conventional EM simulation, which offers far greater speed, full- chip scalability and direct SPICE output, with signoff-level accuracy. A shortcoming of similar techniques has been the inability to model - using passive SPICE elements - the frequency-dependent behavior of conductor resistance due to skin and proximity effects. We are now showing how this can be accomplished by substituting resistors with parallel RL branches. When mutual inductances come into play, RL skin components may result to non-passive netlists; to address this, we introduce a procedure based on eigenvalue decomposition of the inductance matrix, which invariably leads to a passive netlist. This leaves one remaining argument our approach should address: netlist size. To compress large netlists produced by complex layout, we are proposing a technique which groups multiple on-chip metal segments using geometrical criteria and collectively models these with compact RLC pi-networks. Mutual inductances and capacitances among segments are consistently introduced in the model while still retaining the compact size of the final netlist. As a result of all these techniques, full-chip electromagnetic modeling with rapid extraction and simulation times becomes a possibility.
P_6	MOST Modeling for Ultra-thin Flexible Electronics Joachim N. Burghartz, Nicoleta Wacker, Mahadi-Ul Hassan, Horst Rempp, Harald Richter IMS-Chps Abstract:  CMOS transistors on ultra-thin chips for flexible electronics are prone to varying uniaxial/biaxial stress conditions. This talk investigates the physical effects of stress on CMOS transistors fabricated on ultra-thin silicon and the aspects of compact model generation. Particular attention is paid to parameter extraction and the associated measurement techniques. Furthermore, geometry dependence of stress effects will be addressed. The approach is to first establish the required techniques by using the known 4-point bending method and thick silicon strips that are introduced to stress by bending. Ultra-thin (20 µm) silicon chips are exposed to stress in an in-house built stress apparatus. Of particular interest is the question if CMOS transistors on such thin silicon chips behave, and can be modelled, like devices integrated on conventional silicon substrates.
P_7	Guidelines for Verilog-A CM Coding Gilles Depeyrot DOLPHIN Integration Abstract:  Verilog-A has practically become the standard for developing and coding compact device models. However, contrarily to the Verilog standard, where the IEEE has defined syntax and semantic rules for both simulation and synthesis (IEEE1364-2001 and IEEE 1364.1-2002), the Verilog-AMS hardware description language includes extensions dedicated to compact modeling, as a superset, but does not define a subset reserved for compact modeling. This lack of specification combined with some SPICE related specificities, such as the distinction between models and instances, are both responsible for the speed and memory consumption differences measured between Verilog-A compact models running in Verilog-A simulators and the same Verilog-A compact models running in SPICE simulators after conversion of the Verilog-A models into compiled SPICE models. That is the reason why, after presenting these differences, this paper presents recommendations for developers of Verilog-A compact models who want to optimize their models for SPICE-like simulators and to facilitate the integration of said models into different simulators.
P_8	GNU Tools for CM Standardization Paolo Nenzi Uni. Roma Abstract:  The availability of free, reliable and well documented tools is a key issue in the process of defining an open standard for Compact Modeling. The tools should be integrated into a toolchain helping the modeling engineer from data acquisition (from wafer or TCAD) to model deployment into circuit simulators. Such toolchain (implementing the standard) will contribute to the adoption of the standard and, at the same time, will constitutes an open platform for further standardization activities. A survey conducted on the Internet showed that most if, if not all, the tools needed are already available as independent projects, released as free or open software, but they are not integrated, nor conforming to any particular standard. The most promising tools, from the points of view of reliability and possible integration, are presented and a tentative modeling workflow using those tools is shown.
16:00	End of the workshop
Committee	Benjamin Iniguez, URV; Technical Program Chair Matthias Bucher, TUC; ESSCIRC Tutorials and Workshops Chair Charalambos Dimitriadis, Uni Thessaloniki; ESSDERC Tutorials and Workshops Chair Pekka Ojala, Exar; MOS-AK/GSA WG North America Chair Gilson I Wirth; UFRGS; MOS-AK/GSA WG South America Chair Ehrenfried Seebacher, austriamicrosystems AG; MOS-AK/GSA WG Europe Chair Al Kordesch, Silterra Malaysia; MOS-AK/GSA WG Asia/Pacific Chair Chelsea Boone GSA; Senior Research Analyst Darryl Leavitt, GSA; Director of Events Wladek Grabinski, GMC Suisse; MOS-AK/GSA Workshop Manager

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No.#25594

update: Sept.22 2009 (rev. b)

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