Arbeitskreis MOS-Modelle und Parameterextraktion
MOS Modeling and Parameter Extraction Working Group
MOS-AK/GSA Workshop
Dec.9, 2009 Baltimore

Johns Hopkins University at Homewood Campus
in the Computational Sciences and Engineering 
MOS-AK 2009: 20 Years of Enabling Compact Modeling R&D Exchange
 Sponsors and Workshop Organizers
IEEE Baltimore Section ExCom ESD SSCS
IEEE EDS/SSCS Baltimore Chapter
 Technical MOS-AK/GSA Program Promoters
EuroTraining MOSIS
The MOSIS Services
 MOS-AK/GSA Publication Partners
SSE ijnm_wiley
MOS-AK/GSA Workshop Program
Display Format: Citation Citation & Abstract
9:00-12:00 Morning Session
P_1  Compact Models for Organic Field Effect Transistors: Overview and Challenges
Andreas G. Andreou
Johns Hopkins University
P_2  Compact, Equivalent Circuit Models for GaN, SiC, GaAs and CMOS FET
Ilcho Angelov
Chalmers Univ.Goteborg, Sweden
P_3  CMOS Analog Design Using All-Region MOSFET Modeling
Carlos Galup Montoro and Márcio C. Schneider
Federal University of Santa Catarina, Brazil
P_4  Compact Modeling Aided Technology Design and Projection Considering System-Level Performance
Lan Wei, H. -S. Philip Wong
Stanford University (USA)
P_5  Unification of MOSFET Compact Models with the Unified Regional Modeling Approach
Xing Zhou*,**, Guojun Zhu*, Shihuan Lin*, Chengqing Wei*, Junbin Zhang*, Zuhui Chen*, M. K. Srikanth*,**, Ramachandran Selvakumar*,**, and Yafei Yan*,**
*EEE, NTU (Singapore), **ISNE, NTU (Singapore)
P_6  Advances in SOI Compact Modeling
Benjamin Iñiguez and Romain Ritzenthaler
Universitat Rovira i Virgili, Tarragona, Spain
12:00-13:00 Lunch Break
13:00-16:00 Afternoon Session
P_7  A Front to Back Process Variation Aware SPICE Based Design System For Arbitrary EM Devices and Shapes
James Victory, Juan Cordovez and Derek Shaeffer
Sentinel IC Technologies
P_8  Compact Modeling of LDMOS Transistors for Extreme Environment Analog Circuit Design
Avinash S. Kashyap*, H. Alan Mantooth*, Tuan Vo**, Mohammad Mojarradi**
*University of Arkansas, Fayetteville, **Jet Propulsion Laboratory
P_9  Physical models for transistor gate stack degradation processes
Gennadi Bersuker
P_10  Gnucap, a user extendable simulator
Albert Davis
Free Electron Software
P_11  Practical Considerations for Developing, Debugging, and Releasing Verilog-A Models
Marek Mierzwinski, Boris Troyanovsky, and Patrick O’Halloran
Tiburon Design Automation (Santa Rosa, CA)
P_12  Recent achievements in Verilog-A compact modeling
Geoffrey J. Coram and Mengmeng Ding
Analog Devices, Inc. (USA)
Panel Discussion - Moderator: Larry Nagel

  • Compact models QA validation: Still a challenge?
  • Foundries models vs. Verilog-a modeling
17:00 End of the MOS-AK/GSA Workshop
  • Andreas G. Andreou, JHU; Technical Program Chair
  • Pekka Ojala, Exar; MOS-AK/GSA WG North America Chair
  • Gilson I Wirth; UFRGS; MOS-AK/GSA WG South America Chair
  • Ehrenfried Seebacher, austriamicrosystems AG; MOS-AK/GSA WG Europe Chair
  • Chelsea Boone GSA; Senior Research Analyst
  • Darryl Leavitt, GSA; Director of Events
  • Wladek Grabinski, GMC Suisse; MOS-AK/GSA Workshop Manager
update: Dec.22, 2009 (rev.b)
Contents subject to change ©1999-2009 All rights reserved. WG
Graphics © 2009 Oliver