Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
  9th International MOS-AK Workshop
(co-located with the CMC Meeting and IEDM Conference)
December 7, 2016 Berkeley
Open Directory
MOS-AK: Enabling Compact Modeling R&D Exchange 
  MOS-AK Sponsor and Technical Program Promoters
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MOS-AK Workshop Program  
Important Dates:
  • Preannouncement - Sept 2016
  • Call for Papers - Oct. 2016
  • Final Workshop Program - Nov. 2016
  • MOS-AK Workshop - Dec. 7 2016
    • 9:00-12:00 Morning Session
    • 13:00-16:00 Afternoon Session
Venue: 540 Cory Hall
EECS Department
University of California, Berkeley
Display Format: Citation Citation & Abstract
MOS-AK Morning Session
Larry Nagel, Omega Enterprises Consulting (US)
T_0  MOS-AK Intro
Jaijeet Roychowdhury and W.Grabinski
UC Berkeley, MOS-AK
T_1  Custom Silicon for All
Geoffrey Porter
T_2  World-Wide Compact Model Standardization for an Expanding Industry
Peter M. Lee
Micron Memory Japan, Inc.
T_3  Berkeley MAPP: Verilog-A support, multiphysics, table-based models, and other updates
Tianshi Wang, A. Gokcen Mahmutoglu, Archit Gupta, and Jaijeet Roychowdhury
UC Berkeley

Coffee Break
T_4  A Universal SPICE Modeling Approach with Artificial Neural Network
Lining Zhang and Mansun Chan
Hong Kong University of Science and Technology
T_5  Compatibility of Models Among Simulators Facilitated by Verilog-A
Jiang Liu, Eric O'Dell and Larry Dunleavy
Modelithics, Inc.
T_6  Gnucap: Circuit Analysis Package
Albert Davis
Lunch Panel Discussion: GPL/CMC model license compatibility
About CMC Models in OpenSource Simulators
Didier Céli
STM, Grenoble (F)
Xyce Update with CMC Licensing Discussion
Jason  C. Verley
Sandia National Labs (US)
MOS-AK Afternoon Session
Jaijeet Roychowdhury
T_7  Practical Considerations in 1/f Noise Measurements
Raj Sodhi
Keysight Technologies
T_8  Gate Resistance Measurement and Modeling for 3D FETs
Josef Watts, Christoph Schwan, Edward Nowak, Richard Taylor III
T_9  Compact Modeling of Planer Band-to-Band and Vertical Interlayer Tunnel Field-Effect Transistor in Verilog-A for Digital Circuit Design
Ashok Srivastava and Md Fahad
Louisiana State University

Coffee Break
T_10  Modeling of Transition Metal Dichalcogenide Transistors for SPICE Simulation
Chandan Yadav and Yogesh S. Chauhan
Indian Institute of Technology Kanpur
T_11  New generation reliability model
Jushan Xie and Ru Huang
Cadence and Peking University
T_12  TCAD Simulation of Spectral Regrowth in RF Transistors
Chris Morton
16:00 End of MOS-AK Workshop


Extended MOS-AK Committee:
  • International MOS-AK Board of R&D Advisers
    • Larry Nagel, Omega Enterprises Consulting (US)
    • Andrei Vladimirescu, UCB (US); ISEP (FR)
  • MOS-AK Workshop Manager
    • Wladek Grabinski, MOS-AK (EU)
  • MOS-AK Technical Committee
    MOS-AK North America
  • Chair: Pekka Ojala, Exar Corporation (US)
  • Co-Chair: Geoffrey Coram, Analog Devices (US)
  • Co-Chair: Jamal Deen, U.McMaster (CA)
  • Co-Chair: Roberto Tinti, Keysight EEsof Division (US)
    MOS-AK South America
  • Chair: Gilson I Wirth; UFRGS; (BR)
  • Co-Chair: Carlos Galup-Montoro, UFSC; (BR)
  • Co-Chair: Sergio Bampi, UFRGS, (BR)
  • Co-Chair: Antonio Cerdeira Altuzarra, Cinvestav - IPN, (MX)
    MOS-AK Europe
  • Chair: Ehrenfried Seebacher, ams AG, (A)
  • Co-Chair: Alexander Petr, XFab, (D)
  • Co-Chair: Benjamin Iniguez, URV, (SP)
  • Co-Chair: Franz Sischka, SisConsult, (D)
    MOS-AK Asia/South Pacific

  • Chair: Sadayuki Yoshitomi, Toshiba (J)
  • Co-Chair: Min Zhang, XMOD Shanghai, (CN)
  • Co-Chair: Xing Zhou, NTU Singapore (SG)  
  • Co-Chair: A.B. Bhattacharyya, JIIT New Delhi (IN)
update Jan. 2017 (rev. a)
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