MOS-AK/GSA ESSDERC/ESSCIRC Workshop Bucharest

MOS-AK: Over Two Decades of Enabling Compact Modeling R&D Exchange

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MOS-AK Workshop Program

Venue:	JW Marriott Bucharest Grand Hotel Calea 13 Septembrie 90 Bucharest 050726 Romania
	Workshop Agenda
9:00 - 12:00	Morning Session - Chair: Prof. Andrei Vladimirescu, ISEP (F); UCB (USA)
O_1	Welcome and Workshop Opening W. Grabinski MOS-AK Group (EU) Abstract: TBD
K_2	SPICE In The Twenty-First Century Larry Nagel Omega Enterprises Consulting (USA) Abstract: TBD
T_3	NGSPICE: recent progresses and future plans Paolo Nenzi, Francesco Lannutti, Robert Larice, Holger Vogt, Dietmar Warning** DIET - Sapienza University of Roma (I), * NGSPICE Development Team Abstract: In over a decade of existence ngspice has provided the EE community a free, open and reliable circuit simulator based on the Berkeley's spice3 industry standard. Most of known limitations of spice3 are still present in ngspice as they share the same architecture. Removing the remaining limitations requires extensive changes in the simulator's code that should be validated. The electronic designers community needs have changed in the more than 40 years of spice existence. Front of the line research today is on mobile, environment-aware, systems, involving complex interaction between physics, electronics, and electromagnetism (only to cite a few). The following questions arise: it is still spice3/ngspice needed in the development of those systems ? it is worth to move beyond spice3 with a free simulator ? In which directions ? These are the questions that will be addressed, describing the recent progresses in the development of ngspice, the new functionalities implemented and the future lines of development.
T_4	KCL and Linear/NonLinear Separation in NGSPICE Francesco Lannutti DIET - Sapienza University of Roma (I) and NGSPICE Development Team Abstract: This talk will explain: 1) The KCL (Kirchhoff Current Law) Verification implemented in NGSPICE, illustrating methods and laws. This method will give more accurate results and will avoid the False Convergence phenomenon. 2) The Linear and NonLinear Separation in both models and internal components. In addition, a novel algorithm to separate these parts inside the circuit matrix will be presented. This will boost circuits with a lot of linear components, like the back-annotated ones.
	Coffee Break
T_5	Modeling Junction Less FETs Jean-Michel Sallese, Farzan Jazaeri, Lucian Barbut EPFL (CH) Abstract: We present recent developments on modeling activities regarding the junction less double gate MOSFET architecture. This includes long channel charge based modeling and short channel effects corrections, design space analysis for long channel devices based on analytical relationships, and a complete AC model including the 4 independent transcapacitances.
T_6	HiSIM-Compact Modeling Framework Hans Juergen Mattausch Uni. Hiroshima (J) Abstract: TBD
P_7	The Correct Account of Nonzero Differential Conductance in the Saturation Regime in the MOSFET Compact Model Valentin Turin, Gennady Zebrev, Sergey Makarov, Benjamin Iniguez, and Michael Shur*** State University-ESPC (RU),MEPHI (RU),SYMICA Inc (RU),URV (SP),*RPI (USA) Abstract:** We analyze the approaches to account the nonzero differential conductance in the saturation regime in the modern MOSFET compact models. We show that neither entry-level MOSFET compact models, like MOSFET Level 1, nor BSIM3/4 models, that are industry standard, does not provide a monotonic decrease of the differential conductance with increasing drain-to-source bias from high value in linear regime up to nonzero value in saturation regime. In addition, in BSIM3/4 model the differential conductance value at zero drain-to-source bias in case account the nonzero differential conductance in saturation regime can deviates significantly from postulated for the linear regime differential conductance value. To overcome this drawbacks, we suggest a simple and versatile approach for correct account of the differential conductance in the saturation regime that provides a monotonic decrease of the differential conductance from its maximum value to minimum positive or even negative value. We present all equations also in normalized form, that simplify ones analyzes and usage. Based on suggested approach we have developed ``internal'' (does not include source and drain resistance) MOSFET compact model and have incorporated one into EDA software Symica as Verilog-A module.
12:00 -13:00	Lunch Break
13:00 -16:00	Afternoon Session - Chair: W. Grabinski, MOS-AK Group (EU)
T_8	State of the Art Modeling of Passive CMOS Components Bernd Landgraf Infineon Technologies (A) Abstract: The author describes the state of the art of modeling of passive components like poly resistors, diffused resistors and capacitors. An overview focused on parameter extraction and the description of parasitic effects like self-heating, velocity saturation and depletion pinching with the help of the common R3 model will be given. Advantages and disadvantages of different device types will be described as well. Furthermore, accurate modeling of BEOL capacitors will be addressed. Selected practical issues will close this presentation.
T_9	Compact I-V Model of Amorphous Oxide TFTs Benjamin Iniguez,Alejandra Castro-Carranza , Muthupandian Cheralathan* , Slobodan Mijalkovic, Pedro Barquinha, Elvira Fortunato, Rodrigo Martins,Magali Estrada*, and Antonio Cerdeira** URV (SP), Silvaco Ltd (UK), UNL(P), CINVESTAV (MEX) Abstract:** We present a compact model for Amorphous Oxide Semiconductor (AOS) TFTs. The model, called MOTFT, is based on the so-called unified model and extraction method (UMEM), which has been adapted to different types of TFTs. We implemented the MOTFT Verilog-A code in Electronic Design Automation tools (EDA) and it is shown that a good agreement is obtained with experimental data from GIZO TFTs. The model considers three regimes. In the deep subthreshold regime, the drain current is an exponential function of the gate voltage. In the moderate subthreshold regime the current is written as a power function of the gate voltage overdrive. In the above threshold regime, the current is also a power law of the gate voltage overdrive, but with a different exponent. We use interpolation to join the subthreshold and the above threshold regions, we use interpolation functions.
	Coffee Break
T_10	Three-Dimensional Electro-Thermal Circuit Model of Power Super-Junction MOSFET Aleš Chvála, Daniel Donoval, Juraj Marek, Patrik Príbytný and Marián Molnár Institute of Electronics and Photonics, Slovak University of Technology in Bratislava (SK) Abstract: Todayâ€™s circuit simulators are standard tools in the development and optimization of electronic systems. In the power-electronic systems in particular, temperature is one of critical parameters due to the non-negligible self-heating effects and the fact that many properties of power semiconductor devices are strongly temperature-dependent. The standard equivalent models of the power devices for circuit electro-thermal simulations consist of one-dimensional Cauer or Foster type thermal equivalent networks. The one-dimensional heat flow can be insufficient particularly for large power devices and large power pulses. An inhomogeneous temperature distribution caused by three-dimensional heat flow from semiconductor chip to package and cooling assemblies can cause inhomogeneous distribution of electrical properties of the power device along the whole chip. Therefore it is necessary to allocate the structure into several cells with thermal interaction in three dimensions. In this paper we present new electro-thermal model of power MOSFET for circuit simulation, which contains a dynamic link between electrical and thermal components description. The thermal equivalent network for a three-dimensional heat flow is presented. The designed electro-thermal MOSFET model for circuit simulations with distributed properties and three-dimensional thermal equivalent network is used for simulation of multipulse unclamped inductive switching (UIS) test of device robustness. The features and the limitations of the new model are analyzed and presented.
T_11	A Close Comparison of Silicon and Silicon Carbide Double Gate JFETs Matthias Bucher, Rupendra Sharma Technical University of Crete, Chania, (GR) Abstract: TBD
T_12	Towards wide-frequency substrate model of advanced FDSOI MOSFET Sergej Makovejev, Valeriya Kilchytska, Jean-Pierre Raskin, Denis Flandre UCL (B) Abstract: MOSFET small-signal elements vary with frequency. Impact of self-heating on the output characteristics frequency response is well known. However, a substrate effect due to substrate capacitance and hence potential at the BOX-substrate interface variation with frequency is often neglected. This effect is further amplified with BOX thinning in ultra-thin body and BOX (UTBB) MOSFETs. In the most advanced devices, impact of the substrate effect might be stronger than the impact of self-heating. Therefore, for correct MOSFET small-signal representation, a substrate model must be included in the complete equivalent circuit. As in advanced devices the cut-off frequency increases into gigahertz range, the substrate model should be valid up to ~1e12 Hz. In this work, a MOS capacitor representing BOX and the substrate of an advanced FDSOI MOSFET was simulated using Atlas in the 300 â€“ 675 K temperature range. Substrates of advanced FDSOI MOSFETs feature rather complex doping profiles due to ground planes and wells. Silicon doping was uniform with concentration from 1e14 to 1e18 cm-3 for different simulations. Characteristic frequencies were extracted from the capacitance frequency derivative and their corresponding equivalent circuit elements were identified. In accumulation these elements are the oxide capacitance, substrate conductance and capacitance. In inversion, they should be completed by conductance in the quasi-neutral region and space charge region capacitance.
P_13	A Simple GNU Octave-Based Tool for Extraction of MOSFET Parameters Daniel Tomaszewski, Grzegorz Gluszko ITE, Warsaw (PL) Abstract: TBD
16:00	End of the MOS-AK Workshop
Scienttific Coordination:	Extended MOS-AK/GSA Committee

No.#16493

update: OCT 2013 (rev. F)