Arbeitskreis MOS-Modelle und Parameterextraktion
MOS Modeling and Parameter Extraction Group Meeting
organized by
W. Grabinski, Motorola and S. Schmidt, XFab
21 October 2002, XFab, Erfurt, Germany
   9:30-9:35 Welcome and Call to order 
S. Schmidt and W. Grabinski
  9:35-10:00 Introduction to XFAB
Jens Kosch (CTO)
10:00-12:00 Morning Session

Model Accuracy and its Key Parameters - Some Ideas and Discussion Suggestions
  The accuracy and reliability of a model is always an important point for design. The relevant numbers for designer are e.g. Vth0, IdSat, Ron, Gm, (U0, GmMax, KP), Temperature and Voltage coefficients. These are the Key Parameter for accuracy besides the scalability of a model. The presentation will give some global ideas for the characterization of the accuracy of a model besides the simple RMS approach. The basis for comparisons is the so called typical mean characteristics obtained from the "golden wafer".

MOSFET Transconductances -- Analysis with the EKV Model
  A method to measure source-, gate-, substrate- and drain transconductances at all levels of inversion and channel lengths is presented. The EKV MOS transistor model provides an ideal framework for their analysis, from weak to moderate and strong inversion. The new EKV 3.0 MOSFET model shows excellent abilities to represent all transconductances simultaneously.

MOS Model 11
R. van Langevelde, A.J. Scholten and D.B.M. Klaassen
  MOS Model 11 (MM11) is the new compact MOSFET model from Philips. MM11 is a symmetrical, surface-potential-based model, which accurately describes distortion behaviour, making it highly suitable for digital, analog as well as RF circuit design. It furthermore includes an accurate description of all physical effects important in modern/future CMOS technologies, such as a.o. gate tunneling and poly-depletion. MM11 is available in the public domain, and is successfully used within Philips. In this presentation, the physical background of MM11 will be discussed, paying attention to the DC, AC and noise modeling. Next, the parameter extraction of MM11, which is simple and straightforward, will be briefly discussed.

SP: its implementation and its behavior on distortions at Vds=0
L. Lemaitre
  SP is a latest generic compact MOSFET model developed at The Pennsylvania State University. It is surface-potential-based, symmetric, contains no iterative loops anywhere, and has a relatively small number of parameters. The additional features of SP include simple and physical charge model which is consistent with the drain current model and is free from the unphysical behavior at Vds=0. The paper presents the SP model and its implementation using ADMS, a model compiler that that compiles new model directly into a target simulator. The model evaluation results are presented focusing on advanced CMOS applications and behavior on distortions at Vds=0.
12:00-12:30 Poster Session

An open and flexible parameter extraction system for multiple MOS models
  This poster shows key aspects of modern MOS modeling requirements. Evern after the selection of the BSIM3v3 model as a standard MOS simulation model by the Compact Model Council (CMC), many other models are used throughout the semiconductor community and parameters need to be determined for all those models. In addition, a strategy for efficient model parameter extraction with a special emphasis on scalability is illustrated. This leads to a software architecture and a data base concept, which enables modeling engineers to handle the parameter extraction for different simulation models from one common measurement base in a very efficient and flexible way. Finally, the poster shows two principal examples for this strategy in their industrial use.

The Complete Analog Mixed-Signal SoC Flow
G. Clemens 
  Based on the mature and well known Eldo and Modelsim technologies, Mentor Graphics has built a new mixed-signal HDL simulator. It's name is ADVance MS. The new tool supports the broadest spectrum of HDL languages, such as VHDL, Verilog, VHDL-AMS, Verilog-A, C models, IBIS and Spice. This enables circuit designers to do real top-down and bottom-up design. The analog solvers of ADVance MS support a large number of semiconductor models. Mentor Graphics develops this tool in three main directions. First - more language support with Verilog-AMS. Second - high complex transistor level count with ADVance Mach. Third - effective RF Mixed-signal simulation with ADVance RF. The new Mixed-Signal simulators can be used within the Mentor Graphics full custom IC environment or in Cadence.

Design centering and yield optimisation of mmic's with off-chip digital controllers
F. Centurelli, R. Luzzi, G. Scotti, P. Tommasino, A. Trifiletti
  A new methodology to perform yield-oriented design of MMIC's in III-V technologies is proposed. A digital control of MMIC bias, based on process parameter estimation by on-chip auxiliary circuits, allows yield enhancement. The methodology to design the external controller, based on design centering approach and a distance-dependent correlated statistical model of HEMT devices, is presented. The advantages of the new approach will be demonstrated from the viewpoint of design centering theory, which allows straight-forward comparison between the proposed method and previously published yield enhancement techniques. The design of a MMIC for optical digital systems has highlighted a 36% improvement in average yield with respect to previously proposed methodologies.

Modelling of RF LDMOS Transistors Using BSIM3
B. Senapati, K. Ehwald, I. Shevchenko, V. Dykyy, and F. Furnhammer 
  We present a model for LDMOS transistors using BSIM3 for RF applications. The non-standard capacitance behaviour and non-linear LDD resistance of the LDMOS are modelled using a sub-circuit. The sub-circuit contains a standard BSIM3v3 model for the intrinsic MOS, and a JFET to model the pinch-off of the drift-region. In order to model high-frequency response, extra lumped elements are considered for the accurate prediction of the high-frequency characteristics. The LDMOS is fabricated into an advanced industrial 0.25µm BiCMOS process. The gate length, width and finger number is 0.245 m, 0.56 m and 10, respectively. Two-port S-parameters for the frequency range from 2GHz to 20GHz are measured for different bias conditions using an HP 8510 network analyzer. The extraction and optimization of model parameter is performed from the measured data of the LDMOS using ICCAP software. The circuit parameters are extracted after open and short de-embedding the probe-pad parasitic. The usefulness and accuracy of the LDMOS model are demonstrated by way comparison of simulation and measured device data at room temperature. 

Infinity RF probes for CMOS and SiGe characterization [Part 1, Part 2]
A. Lord 
  The evolution of silicon CMOS and SiGe technologies now enables designers to address many new RF applications. Devices with aluminium pads are much more difficult to probe than devices with gold pads, which are typically on III-V semiconductors. The series contact resistance due to the resistive oxide on the aluminium pads and traditional Tungsten probes effects both the DC and RF performance of the device and also leads to inconsistent results. Cascade Microtech has developed a new technology, the Infinity Probe, that offers both high-frequency performance and low (< 0.05 Ohms), stable contact resistance on aluminium pads. The Infinity Probe sets a new standard for the device characterization and modeling community. 
12:30-14:00 Lunch
14:00-16:00 Afternoon Session

Extrinsic capacitance model for advanced MOSFET design
  In mixed circuit simulation, the estimation of the extrinsic capacitance of deep-submicron MOSFETs is very important. With the continuous scaling of the devices, the extrinsic capacitance (i.e. overlap plus fringing capacitances) is a growing fraction of the total gate capacitance and thus a correct modeling is required. We present a new approach for modeling this capacitance in the zero-current regime. The bias dependence of each components of the extrinsic capacitance is investigated. Key technological parameters as the LDD doping dose are also studied. Then, we propose an efficient, simple and continuous model describing the evolution of the extrinsic capacitance in all MOSFET operating regimes. This model is finally incorported in an existing compact-model for circuit simulation and leads to excellent results in comparison with full 2D numerical simulations.
Parameter Matching of Active Passive Devices
  Matching - Mismatch, Reasons, Model, Hard & Software
Resistor & Contact Matching, MOS Transistor Matching
Bipolar Transistor Matching, Capacitor Matching
Recommendations for Improvement of Matching
Plans for the Future

RF-CMOS active inductors and their application
  A differential CMOS active inductor is presented. The circuit is realized in a 0.25 µm CMOS-technology with a supply voltage of 2.5 V. A self-resonant frequency of 5.6 GHz is achieved. The measured value of the inductance L can be tuned in the range from 3.2 nH up to 23 nH. The quality factor Q can be tuned independently of the inductance L. The inductive behaviour is achieved by a differential gyrator structure. The gyrator transforms intrinsic capacitances of the MOSFETs to the emulated inductance. A switchable bandpass amplifier in a 0.18 µm CMOS-technology with a supply voltage of 1.8 V is presented as an application example. The circuit features 16 dB gain and a selectable bandpass frequency of 100 MHz or 1 GHz.

The look-up table approach and its applications to MOS transistors and circuits (updated)
  In this paper, the focus is on the use of the look-up table (LUT) approach to (i) evaluate MOS transistor models and (ii) predict circuit performance with novel technologies. The first application is based on the fact that the LUT model happens to serve as the "exact" quasi-static (QS) model, without any approximations. Thus, if one can extract accurately the tables of terminal currents and charges from experimental measurements or device simulation, an exact QS model of the device is obtained. One can perform simulations with this exact QS model either in the time domain or in the frequency domain and compare the results with the actual quantities obtained from experimental measurements or device simulation. This comparison would reveal exactly the role played by NQS effects. For the second application, we take advantage of the fact that the LUT approach is a general one, not requiring implementation of an analytic device model. This is particularly attractive in exploring novel technologies where device models may not be readily available. Some results for circuits involving high-K dielectric gate MOS transistors will be presented. The implementation of the LUT approach in the public-domain circuit simulator "SEQUEL" will be discussed in detail. 
16:00-16:30 Organizational topics
  • organization issues
  • next meeting planning
  • special modeling meetings/tutorials
  • 16:30 Adjourn. End of meeting
    back to MOS-AK
    Contents subject to change.©2002 All rights reserved. WG