Nanocrystalline and ultrananocrystalline diamond combines the remarkable properties of conventional diamond, such as extreme hardness and wear resistance. Here, we report on the correlation between grain size and relevant physical and chemical properties of phase pure NCD and UNCD layers synthesized by chemical vapour deposition on silicon single crystal wafers with diameters up to six inches. The UNCD films consist of ultra-small (ca. 5 nm) equiaxed grains resulting in ultra-smooth surfaces with surface roughness equivalent to the grain size. The mechanical properties show that due to the large number of grain boundaries with highly disordered atomic structure the Young’s modulus is decreased from about 1010 GPa to 500-700 GPa and fracture strength is increased from 1 GPa to ca. 5 GPa. The electrically conductive UNCD layers exhibit a piezoresistive effect which makes it useful for sensing applications. As a step further, by a combination of photolithographic masking and controlled reactive ion etching processes, complex shaped microparts are designed and fabricated. Some applications will be discussed, such as a prototype silicon-diamond hybrid pressure sensor for harsh environments.

Organic thin-film transistors (OTFTs) are commonly used as the basic building blocks for low-cost large-area electronic circuit applications such as foldable information displays, plastic circuits, printed bio-sensing configurations and active-matrix organic light-emitting diode (AMOLED) displays. Process variability during OTFT fabrication, introduces variations into the transistor’s main electrical parameters namely threshold voltage, mobility and channel dimensions. Consequently, circuit properties are affected accordingly. Monte Carlo (MC) simulation is commonly used to determine the performance of OTFT based circuits versus parameter variability. MC consists of a sequential number of simulations where for every iteration, a parameter set is randomly varied and the circuit is simulated accordingly. Subsequently, the statistical results are collected and the yield of the circuit is estimated. For reliable approximations, MC analysis requires a large number of iterations resulting into a significantly increased processing time. Here, a MC alternative for fast statistical circuit analyses will be presented. The proposed method is based on circuit noise simulation principles and can be abbreviated as NOVA (Noise Based Variability Approach). NOVA is applied in OTFT based circuits for both process and mismatch statistical analysis study. Overall, NOVA circuit analysis can be used effectively for Gaussian shaped statistical distributions and presents significant time improvement when compared to the conventional MC simulation.

Today, MOS transistors in new technologies are aggressively scaled. In these devices tunneling currents became more important. Source-to-drain tunneling in ultra-short-channel MOSFETs contributes to their leakage current. Furthermore, new device concepts as e. g. the Tunnel-FET are under investigation, in which tunneling currents are beneficially employed as the dominating type of carrier transport mechanism. Compact modeling must provide numerically efficient solutions to describe tunneling currents in a framework for circuit simulation, preferably while keeping physical insight. In this talk approaches for physics-based and numerically efficient calculation of tunneling currents are reviewed (WKB, Wavelet and NEGF) and their benefits for compact modeling evaluated.

Gallium Nitride (GaN) technology is on the verge of industrial utilization in the fields of power electronics and high-frequency technology. Due to its advantages like high breakdown voltage, low on resistance and high operating temperature. They have potential to be used in THz frequency region. This creates a new demand for special and new characterization and modelling methods. The reason behind this is the complex crystal structure formed by electronegative Ga and N atom. Modeling all the real device effects is a challenge. This is where the project “GaNScan” funded by the German Federal Ministery of Education and Research comes into the picture. A partial aim of this project is to further develop and improve the industry standard model (Compact Model Council-CMC) ASM-HEMT. There are mainly three project partners involved in this project: IMS Chips Stuttgart, RoodMicrotec GmbH and AdMOS GmbH. Within the scope of this project, various advancements in the simulation model have been identified and published. Enhanced or new equations for important aspects like device temperature scaling, gate length scaling and surface potential-based device performance were developed and implemented in the Verilog-A code of ASM-HEMT. Experimental data from several sources allowed a verification of all mentioned improvements. Success of GaNScan project will further strengthen the base of future developments in the field of GaN device simulation models and hence GaN device circuit designs.

Currently optimized circuit design suffers from the lack of accurate and robust models for vertical structure power transistors, and designers often encounter problems in terms of platform compatibility and interchangeability of the vendor models. On the other hand, for CMOS logic devices, industry standard compact models, like the BSIM and EKV family, are proven to be accurate and robust. However these standard models cannot be directly applied to the power devices , since the device structure of power MOSFETs (vertical, trench-MOS) is typically very different from standard CMOS type transistors (lateral) for logic processing. This work presents a modeling approach adopting the industry standard model BSIM3.3 and EKV2.6 with specific structural for a Si vertical power MOSFET. The standard models, which are developed for CMOS logic devices, are evaluated and adopted to describe the channel behavior of the power MOSFETs, and their performances are compared. Meanwhile, the extended components including the non-linear drift resistance, body-diode and drain-gate capacitance are defined according to the vertical MOSFET structure which is different from conventional CMOS devices. The temperature-dependent parameters in the original standard model expressions are used to contribute to an improved dynamic thermal model, which describe the thermal behavior of the device more close to the realistic power transistor operation. The parameters of the model are extracted based on the measurement of the characteristics of the device. The static characteristics are measured by a curve tracer. Considering the frequency dependency of the intrinsic capacitances of power MOSFETs, the capacitance characterization is based on a 2-port S- parameter measurement. A suitable parameter extraction procedure is defined to efficiently extract the model parameters. The parameter extraction result shows that the proposed model is able to describe the device characteristics precisely.

This talk will give an overview of Gnucap, the GNU Circuit Analysis Package, with emphasis on current work, including plugins and "modelgen", the model compiler.

Device characterization is typically based on several measurement instruments that need to be controlled. Then, the ready-to-use software of each manufacturer does not help much as it cannot control the other instruments. As a consequence, one has to start programming. For many institutes and companies, it is not easy to create and maintain a characterization software that can quickly adapt to the needs of the current project and that is versatile enough to cover a wide range of tasks. Here, our measurement software SweepMe! (sweep-me.net) can be a way out. It provides a platform for combining modules of each instrument type, such as ‚SMU‘, ‚Wafer prober‘, ‚Network analyzer‘, or ‚LCRmeter‘. Equipment can be implemented via an open python interface and existing drivers are shared open-source. Once an instrument is implemented, even people with no or little programming skills can create characterization procedures like an on-wafer transistor testing in short time. All users create their procedures by combining and configuring our ready-to-use modules. Therefore, everybody benefits whenever content is improved or added. Our approach also fosters the interaction between institutes and companies in order to create common characterization procedures as a equipment can easily be interchanged. Additionally, we provide a package for the open-source community that allows to create own programs based on our drivers.

The energy level alignment between organic semiconductors and the respective (metal) electrodes in organic electronic devices is of key importance for efficient charge carrier injection. For many years, researchers have attempted to control this energy level alignment by means of functional self-assembled monolayers (SAMs) or the insertion of thin injection layers (made e.g. of doped organic semiconductors or pure dopants). An alternative to these approaches is the use of organic small molecule monolayers as contact primers which are deposited onto noble metal electrodes by means of vacuum deposition. We show that polar as well as non-polar phthalocyanines modify the work functions of clean Au(111) and Ag(111) surfaces as a function of their coverage and thus enable quantitative control of the metal work functions. This behaviour is successfully replicated for polycrystalline metal surfaces and it is found that full monolayers can even withstand air exposure.

The energy level alignment between organic semiconductors and the respective (metal) electrodes in organic electronic devices is of key importance for efficient charge carrier injection. For many years, researchers have attempted to control this energy level alignment by means of functional self-assembled monolayers (SAMs) or the insertion of thin injection layers (made e.g. of doped organic semiconductors or pure dopants). An alternative to these approaches is the use of organic small molecule monolayers as contact primers which are deposited onto noble metal electrodes by means of vacuum deposition. We show that polar as well as non-polar phthalocyanines modify the work functions of clean Au(111) and Ag(111) surfaces as a function of their coverage and thus enable quantitative control of the metal work functions. This behaviour is successfully replicated for polycrystalline metal surfaces and it is found that full monolayers can even withstand air exposure.

Reconfigurable field-effect transistors (RFETs) are devices for dynamically switching between n- and p-typepolarity which enables different logic computations using the samehardware. A simplified single-gate (SG) RFET design is presented which achieves the same functionality and dc characteristics as DG-RFET. Permeable Base Transistors (OPBTs) are of great interest for flexible electronic circuits as they offer very large on-current density and a record-high transition frequency. Stable and reproducible DC characteristics can be expectedand achieved regardless of statistical variation inthe fabrication of the base layer in OPBTs in terms of adeviation of pinhole diameter and density.

In this paper the simulation and modeling of semiconductor devices in MEMS, by Bosch, one of the world’s largest supplier of micromechanical sensors in automotive and consumer applications, is briefly introduced. The simulation and modeling is one of the key elements to bridge the different domains between process technology, electronics, system and customers needs. The here presented methodology ensures an integration from various perspectives. Example of typical Sensor/MEMS design including various mechanical and electronical constraints is given.

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Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes; thru the MOSFET, FDSOI, FinFET and TFET compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present two FOSS CAD simulation and design tools: ngspice and Qucs. Application and use of these tools for advanced IC design (e.g. analog/RF IC applications) directly depends the quality of the compact models implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the transistor level and then trigger further discussion on the compact/SPICE model Verilog-A standardization and development supporting FOSS CAD tools.

During the past decade, 2D (two-dimensional) materials have attracted enormous attention from various scientific communities ranging from chemists and physicists to material scientists and device engineers. The rise of the 2D materials began in 2004 with the work on graphene done at Manchester University and Georgia Tech. Particularly the observed high carrier mobilities raised early expectations that graphene could be a perfect electronic material. It soon became clear, however, that due its zero bandgap graphene is not suitable for most electronic devices, in particular transistors. On the other hand, researchers have extended their work to 2D materials beyond graphene and the number of 2D materials under investigation is continuously rising. Many of these materials possess sizeable bandgaps and therefore may be useful for transistors. Indeed, the progress of research on 2D transistors has been rapid and MOSFETs with semiconducting 2D channels have been reported by many groups. A recent achievement was the demonstration of a 1-nm gate MoS2 MOSFET in 2016. Moreover, other types of 2D devices such 2D memristors, 2D sensors, and 2D devices optoelectronics are currently under investigation. In the present lecture, the most important classes of 2D materials are introduced and the potential of 2D transistors is assessed as realistically as possible. To this end, two key material properties – bandgap and mobility – are examined in detail and the mobility- bandgap tradeoff is discussed. The state of the art of 2D transistors is reviewed by summarizing relevant results of leading groups in the field and by comparing the performance of 2D transistors to that of competing conventional transistors. Based on these considerations, a balanced view of both the pros and cons of 2D transistors is provided and their potential in digital CMOS and in other domains of semiconductor electronics is discussed. It is shown that due to the rather conservative CMOS scaling scenarios described in the most recent ITRS and IRDS editions (compared to the more aggressive scenarios of previous ITRS editions), in the near-to-medium term it will be difficult for 2D materials to make inroads into mainstream CMOS. However, research on beyond-CMOS 2D devices has led to promising results. Exemplarily, the status and prospects of 2D sensors and 2D memristors is discussed.

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Vertical organic transistors with a channel length of <300nm are ideally suited for high - frequency operation of flexible electronics devices. Here we present organic permeable base vertical organic transistors integrated into complementary circuits which show a rise and fall time of only 5ns in inverter circuit operating at <3V. These devices require high - quality Schottky - contacts to reach a high gain, device stability, and subthreshold slope.