Abstract: 
This presentation outlines the compact modelling and simulation features implemented in the Qucs-S and QucsStudio circuit simulators, paying particular attention to Verilog-A as a vehicle for device modelling and model interchange. Individual topics include: Background, Equation-Defined Device and Verilog-A modelling, Qucs-S Verilog-A synthesis, Built-in Verilog-A modules, CMC and others, Verilog-A Equation-Defined Device prototyping, Enhanced Qucs-S/Xyce behavioural compact modelling and future developments. The performance of the Qucs-S/QucsStudio modelling and simulation packages will be demonstrated using a series of compact modelling examples based on semiconductor technologies.
Bio: 
Mike Brinson received a first class honours BSc degree in the Physics and Technology of Electronics from the United Kingdom Council for the National Academic Awards in 1965, and a PhD in Solid State Physics from London University in 1968.  Dr. Brinson has held academic posts in Electronics and Computer Science.  From 1997 till 2000 he was a visiting Professor of Analogue microelectronics at Hochschule, Bremen, Germany.  Currently, he is Professor at the Centre for Communications Technology Research, London Metropolitan University, UK.  He is a Chartered Engineer (CEng) and a Fellow of the Institution of Engineering and Technology (FIET), a Chartered Physicist (CPhys), and a member of the Institute of Physics (MInstP).  Professor Brinson joined the Qucs project team in 2006, specialising in modelling and testing.  Professor Brinson regularly contributes to the MOS-AK meetings.

Abstract: 
The recent development in neuromorphic computing has generated a strong demand for memory array simulation.  However, the conventional approach to simulate logic circuit is not memory friendly and memory models have to work around a number of fundamental limitations before they can be used in circuit simulator.  In this presentation, I will discuss the simulation infrastructure required for neuromorphic computing and the approach to develop memory models that can handle detail temporal variations with respect to in-coming signals and data.
Bio: 
Prof. Mansun Chan received his PhD from the University of California at Berkeley. Subsequently, he joined the Hong Kong University of Science and Technology and he is now the Alex Wong Siu Wah Gigi Wong Fook Chi Professor of Engineering and Chair Professor of the Department of Electronic and Computer Engineering. He was one of the major contributors to the unified BSIM model for SPICE, which has been accepted by most US companies and the Compact Model Council (CMC) as the first industrial standard MOSFET model. His current research interests include emerging nano-device technologies, 2-D device for flexible electronics, CMOS interconnect technology, Artificial Neural Network systems, new-generation memory technology, BioNEMS, device modeling and ultra-low power circuit techniques. He is a Distinguished Lecturer of IEEE, Fellow of IET and Fellow of IEEE.

Abstract: 
This is a collection of slides presenting an accurate compact model for organic TFTs, which proved to be valid above threshold. This model has a physical basis and allows an easy parameter extraction. The model parameters have a technological meaning and can be introduce in a numerical 2D TCA device simulator. The mobility model has been extended to the nonisotropic case. The new OTFT model has been incorporated into the standard Verilog-A code
Bio: 
Benjamin Iñiguez obtained the Ph D in Physics in 1992 and 1996, respectively, from the Universitat de les Illes Balears (UIB). From February 1997 to September 1998 he was working as a Postdoctoral Researcher at the Rensselaer Polytecnhnic Institute in Troy (NY, USA). From September 1998 to January 2001 he was working as a Postdoctoral Scientist in the Université catholique de Louvain (Louvain-la-Neuve, Belgium), supported by two Marie Curie Fellowships from the European Commission. In February 2001 he joined the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA)of the Universitat Rovira i Virgili (URV), in Tarragona, Catalonia, Spain) as Titular Professor. In February 2010 he became Full Professor at URV. He obtained the Distinction from the Generalitat for the Promotion of University Research in 2004 and the ICREA Academia Award (the highest award for university professors in Catalonia, from ICREA Institute) in 2009 and 2014, for a period of 5 years each. He led one EU-funded project (“COMON”, 2008-12) devoted to the compact modeling of nanoscale semiconductor devices and he is currently leading one new EU-funded project (DOMINO, 2014-18) targeting the compact modeling of organic and oxide TFTs. His main research interests are the characterization, parameter extraction and compact modelling of emerging semiconductor devices, in particularorganic and oxide Thin-Film Transistors, nanoscale Multi-Gate MOSFETs and GaN HEMTs. He has published more than 150 research papers in international journals and more than 130 abstracts in proceedings of conferences.

Abstract: 
With the advances of CMOS technologies and their use for various low power analog and digital applications, some additional effects must be modeled or enhanced to improve the accuracy of the SPICE models. Indeed, with the decrease of supply voltages/currents and the use of the back bias in Fully-Depleted Silicon On Insulator (FDSOI) technologies, the devices operate close to the weak-moderate inversion, where gm/Id figure is impacted by effects like the depletion of source/drain electrodes. In addition, parasitic currents, such as Impact ionization current in moderate inversion regime and gate leakage current in weak inversion, can have a significant impact on the model accuracy. In this presentation, we will describe the latest significant improvements of L-UTSOI model (formerly Leti-UTSOI), from the physical background of these developments to their validation against silicon experimental data.
Bio: 
Sébastien Martinie received the M.S. degree in electrical engineering from the École Polytechnique Universitaire de Marseille, Marseille, France, in 2006, and the Ph.D. degree from the University of Aix-Marseille, Marseille, in 2009. He has been with CEA-Leti, Grenoble, France, since 2012, as a Device Engineer. He is currently working on the introduction of advanced carrier transport in compact models for circuit simulation with nanoscale field-effect transistors. In CEA-Leti compact modeling team, Sébastien is in charge of the developments of L-UTSOI standard model.

Abstract: 
This talk will report on ngspice, the open source spice circuit simulator, covering three major topics:  The ngspice simulator core currently is getting several updates. UNICODE support and vastly improved graphics are available. The KLU matrix solver is under final testing.  ngspice co-operates with third party schematic entry tools. KiCad for discrete electronics and XSchem for IC work will be discussed.  The power MOS VDMOS model has got a major uplift. Modeling of self-heating has been added, enabling electro-thermal simulation for power electronics. The the bipolar HICUM model will be directly integrated into the ngspice C code.
Bio: 
Holger Vogt received the Diploma degree in electrical engineering and the Dr.-Ing. degree from the University of Dortmund, Dortmund, Germany, in 1981 and 1986, respectively. Since 1985, he has been with the Fraunhofer Institute of Microelectronic Circuits and Systems (IMS), Duisburg, Germany, where he is currently the Deputy Director. He is responsible for the institute’s R&D strategy and engaged in the acquisition of large projects. He was responsible for establishing a 200-mm CMOS fabrication facility at IMS and for CMOS process development and has been heading a cleanroom facility for the co-integration of MOEMS and CMOS, dedicated to post-processing for compact microsystems on top of “intelligent” CMOS substrates. He is also a Professor with the Department of Electrical Engineering and Information Technology, University of Duisburg-Essen, Duisburg.

Abstract: 
In this talk, we first briefly review the BCD technologies that power up all mobile devices. Such technologies have also been widely used in automotive, healthcare, and industry. One of the key devices in BCD is LDMOS that handles high voltage. We review LDMOS modeling methods and challenges associated with halo doping and non-uniform lateral channel doping. We then introduce our recently developed and publicly accessible model PSPHV. It consists of a PSP model for the MOS channel and a dual-gate JFET model, JFETIDG, for the drift region. We explain how PSPHV overcomes the challenges. Finally, we explain the PSPHV model extraction flow.  
Bio: 
Dr. Kejun Xia received the Ph.D. degree in Electrical Engineering at Auburn University in Dec. 2006. After graduation, he joined Maxim Integrated R&D department, where he served as a Senior Principal Member of Technical Staff leading the modeling activities for the advanced BCD & SiGe BiCMOS technologies. From 2014 to 2015, he was with the Analog & Sensor BU at Freescale Semiconductor as a modeling manager, where he expanded his experience to modeling ESD, Reliability, MEMS, product behavior model, etc. From 2016 to 2019, he was with NXP semiconductor as a modeling manager, where he is also responsible for certain fab transfer projects. Since 2020, he manages the US HV and analog technology development team in NXP. Dr. Xia’s research interests include device physics; process; compact modeling; model and its interaction with analog circuits. He is a senior member of IEEE. He has published many technical papers in renowned journals and conferences. He has been a frequent reviewer for IEEE Transactions on Electron Devices, IEEE Electron Device Letters, and Solid-state electronics. He has served as a guest editor for IEEE TED and JEDS special issues. He has been on the technical program committees for the IEEE EDTM conference. He is a member of IEEE compact modeling committee.

Abstract: 
Ion Sensitive Field-Effect Transistors (ISFETs) are being continuously improved for advanced use in medical personalized care as bio-chemical sensors. The junctionless (JL) nanowire (NW) ISFET, is uniformly doped nanowire in electrolyte medium having no junctions nor doping gradients for source and drain contacts, leading to simplified fabrication technology. Here we introduce deep theoretical analysis of JL ISFET self-consistently combining the electro chemical interaction between the semiconductor-insulator interface and the surrounding analyte and predict the output characteristics of JL NW ISFETs with respect to pH. These developments are fully validated with COMSOL Multiphysics simulations and suitable for implementation in circuit simulators.
Bio: 
Ashkhen Yesayan is a senior researcher and scientific secretary at Institute of Radiophysics and Electronics National Academy of Sciences in Armenia. She obtained a Ph.D. degree in physics from Yerevan State University, in 2005. After the PhD defense she was a postdoctoral researcher at University of Pisa, and later, as a Marie Curie associate (postdoctoral researcher) at the University of Strasbourg, 2009-2011. As a visiting scientist, she twice has been at EPFL, in Electrical Department. Her current research activities cover compact modeling of nanowire and double-gate junctionless ion-sensitive FETs, modelling of core/shell nanowires, photovoltaic nanowire devices and nanoscale memristors.