Arbeitskreis
MOS-Modelle und Parameterextraktion MOS Modeling and Parameter Extraction Working Group MOS-AK/GSA Workshop March 16-18, 2012 India |
In Collaboration with |
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INDIAN NATIONAL ACADEMY OF ENGINEERING |
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MOS-AK/GSA Workshop Sponsors |
Platinium
Sponsors |
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Gold Sponsors | |||
DIT |
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Silver Sponsors | |||
Technical MOS-AK/GSA Program Promoters |
IEEE EDS Chapter Delhi |
The MOSIS Services |
MOS-AK/GSA Workshop |
Venue: | Jaypee Institute of
Information Technology (JIIT), A-10, Sector-62, Noida (U.P.), India Phone: 0120-2400973-976, 2400987 |
Technical Workshop
Poster Session Program |
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Poster
Session |
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P-1 |
Compact Model
based Efficient Methodology for Successful Technology Transfer A.N. Chatterjee, V.N. Vanukuru ,S. Parthasarathy, IBM, D3 MEBP, Nagawara, ORR, Bangalore – 560045 |
P-2 |
MOSFET Modeling
and Parameter Extraction for Low Distortion Analog Circuits operating
in Triode Region Subhajit Sen, DA-IICT, Gandhinagar, Gujrat |
P-3 |
Electro-Thermal
Modeling in Metallic Carbon Nanotube Interconnects Rekha Verma, Sitangshu Bhattacharyya and Santanu Mahapatra Indian Institute of Science, Bangalore, 560012, India. |
P-4 |
Small Signal
Modeling and Parameter Extraction Technique for Overlap and Underlap
Double Gate MOSFET for RF Circuit Design Saptak Niyogi 1, Kalyan Koley 1, Chandan Kumar Sarkar 1, Soumya Pandit 2 1. Jadavpur University, 2. IRPE,Kolkata. |
P-5 |
Analytical Study
of Vertical Channel Engineering Approaches for Reduction of Threshold
Voltage Variation for Low Power Applications Arka Dutta 1, Chandan Kumar Sarkar 2, Samar K. Saha 2, Soumya Pandit 3, 1.Jadavpur University, 2.Su Volta Inc ,Las Getos, USA, 3. IRPE,Kolkata. |
P-6 |
Look-up Table
based Automated FinFET Circuit Design R. A. Thekker 1, Chaitanya Satne 2, Maryam Shojaei 3, M.B. Patil 3 1.EC Department, VCFC, Gandhinagar. Gujrat; 2.EE Department , University of Illonis, Urbana, USA; 3. EE Department, IIT Mumbai |
P-7 |
On-Chip
Interconnect Compatible Physical Modeling of RF Spiral Inductors Vibhu Srivastava, A.B. Bhattacharyya, Jaypee Institute of Information Technology, Noida, U.P. |
P-8 |
Design of High
Precision CMOS Bandgap Reference and Simulation across PVT Corners Hari Shanker Gupta 1, Jayesh Jayaran 1, Sanjeev Metha 1, Sandip Paul 1, R.M. Parmar 1, D.R.M Samudraiah, Dr.Dinesh Kumar Sharma 2 1.ISRO Ahmedabad, 2. IIT, Mumbai, |
MOS-AK India Committee | |
Committee: | International Advisory Committee:
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