Joint ESSDERC/ESSCIRC Tutorial: Nanoscale Technology – Transistor Modeling – IC Design
Wladek Grabiński (GMC, CH)
Daniel Tomaszewski (ITE, PL)
Venue: Exhibition Room
Our joint ESSDERC/ESSCIRC Tutorial aims to provide in-depth coverage of highly relevant R&D topics by world-class experts. We will discuss and present the frontiers of electron device modeling with emphasis on the complete UT SOI development chain, reviewing the nanoscale level technologies, devices TCAD numerical simulations, thru its simulation-aware compact/SPICE modeling up to selected topics of the transistor level IC design for advanced applications. This joint tutorial is designed for academic researchers, device process engineers who are interested in device modeling; academic/industrial ICs designers (to explore RF/Analog/Mixed-Signal) and those starting in these areas as well as device fabrication, electrical characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind the IC fabrication and its simulation in using modern SPICE/Verilog-A device models.
8:00 – 8:30 – Registration
8:30 – 9:15 – Technology: Guillaume Besnard, SOITEC (F) – UT SOI Processing and Device Fabrication
9:15 – 10:00 – Technology: Ahmed Nejim, Silvaco Inc. (USA) – UT SOI TCAD Numerical Process/Device Simulation
10:00 – 10:30 – Coffee break
10:30 – 11:15 – Devices: Thierry Poiroux, CEA–Leti (F)- Compact modeling for FDSOI technologies: Main challenges and possible solutions
11:15 – 12:00 – Devices: Roberto Murphy, INAOE (MX) – RF Electrical Characterization
12:30 – 14:00 – Lunch
14:00 – 14:45 – Design: Christian Enz, EPFL (CH) – Systematic Design of Low-power Analog/RF CMOS Circuits using the Inversion Coefficient
14:45 -15:30 – Design: Humberto Andrade da Fonseca (Cadence, US) – Advanced SOI Design and Reliability/Ageing Simulations
15:30 – 16:00 – Coffee break
16:00 – 17:00 – Panel discussion
Speaker 1: Guillaume Besnard, SOITEC (F)
Title: UT SOI
Processing and Device Fabrication
Abstract:
In this course, we will review the FDSOI manufacturing
flow starting from SOI substrate fabrication up to the circuit ready
for test, alongside available options for device integration in
sub-28nm technologies. We will also cover future challengers in
processes, manufacturing tools and environment of advanced CMOS
technologies. Finally, we’ll give a brief outlook of where the
semiconductor industry is going based on current development trends.
Bio:
Guillaume Besnard joined SOITEC in 2012. Today, he
belongs to R&D Collaboration Platforms group and is currently
assigned at IMEC research center (Belgium), managing R&D
programs in Logic, RF/Analog and Photonics. He received the Ph.D degree
in Semiconductor Engineering from Institut National Polytechnique de
Grenoble, France in 2016.
Speaker 2: Ahmed Nejim, Silvaco Inc. (USA)
Title: UT SOI
TCAD Numerical Process/Device Simulation
Abstract:
Device and circuit design activities sit at the heart of technology
development. Technology Computer Aided Design (TCAD) simulation is a
powerful tool used to explore new process flows and device
architectures. The ability to parametrise these simulations, allows
users to effectively explore the available design space and optimise
technology. Issues such as channel design, contact performance,
transient behaviour and parasitic elements can all be captured in this
activity. Furthermore, such simulation can be part of the development
of SPICE models much needed for circuit and system design. SOI
technology with ultra thin buried oxide and fully depleted operation
offers significant advantages for low power applications. However
issues such as parasitic elements as well as thermal effects are
crucial considerations for the design activities. These coupled effects
are inherently considered in the modelling of these devices in order to
capture their full function. The talk will illustrate the numerical
approach used in TCAD to showcase its value.
Bio:
Ahmed Nejim (male) obtained his PhD in 1990 in Ion-Solid interaction. A
wide experience in ion implantation and semiconductor processing was
obtained in 17 years of research in material science, semiconductor
physics and microelectronic design. Experience in lecturing, mentoring
and facility management. 10 years of technical project management,
European multinational projects, Liaison research fellow of a UK
national research facility in contact with national industry and
national and international academia. Since 2001 he has been working at
Silvaco supporting TCAD software users and developing collaborative
projects. He acts as an R&D Project Manager for Silvaco Europe.
Speaker 3: Thierry Poiroux, CEA–Leti (F)
Title: Compact
modeling for FDSOI technologies: Main challenges and possible solutions
Abstract:
Fully-Depleted Silicon-On-Insulator (FDSOI) technologies featuring
Ultra-Thin silicon Body and Buried oxide (UT-SOI) have now entered into
industrial production stage. These technologies present several
decisive advantages over other options, such as excellent transistor
electrostatic control, very low variability, simple planar process
close to that of conventional bulk one, and very efficient back-bias
effect. This latter feature allows a significant dynamic modulation of
delay/power trade-off, which is a powerful know at circuit level.
Therefore, to take full advantage of these technologies, circuit
designer need compact models able to describe the transistor behavior
over wide ranges of applied back biases, which actually requires
considering FDSOI transistor as real Independent Double Gate (IDG)
MOSFETs. In this tutorial, we will review the challenges that are to be
addressed in order to build such compact models, from surface potential
calculation to complete DC, AC and noise models.
Bio:
Thierry Poiroux received the M.S. degree from Ecole Centrale Paris,
France, in 1995 and the Ph.D. degree from the University of Nantes,
France, in 2000. His Ph.D. work was carried out at the Commissariat à
l’Énergie Atomique/Laboratoire d’Electronique et de Technologie de
l’Information (CEA–Leti), Grenoble, France, and Matra MHS on plasma
process-induced damage. In 2000, he joined CEA–Leti as a Research Staff
Member. Until 2002, he was involved in partially and fully depleted
silicon-on-insulator (SOI) process integration and compact modeling.
From 2002 to 2007, he worked on advanced device architectures and was
in charge of multiple-gate device modeling and planar double gate
process integration. In 2007, he started an activity on device
integration on graphene, a promising material for the beyond
complementary metal–oxide–semiconductor era. In 2011 and 2012, he has
been the Head of the Innovative Device Laboratory of CEA–Leti. From
2012 to 2018, he worked on the development of the second version of
Leti–UTSOI compact model, dedicated to fully-depleted SOI technology.
Since 2018, he is the Head of the Simulation and Compact Model
Laboratory of CEA–Leti. He has authored or coauthored five book
chapters and more than 170 papers and communications, and he is author
or co-author of about 20 patents.
Speaker 4: Roberto Murphy, INAOE (MX)
Title: RF
Electrical Characterization
Abstract:
This talk will focus on the challenges involved in the characterization
of MOS transistors in the high frequency regime, especially those
related to calibration and de-embedding techniques. These aspects are
of fundamental importance to define correct compact models for very
high frequencies and smaller devices, as calibration standards deviate
from ideal behavior, de-embedding techniques have to be based on more
realistic structures, and user errors have to be minimized. Some
guidelines to partially overcome these limitations are presented and
discussed.
Bio:
Roberto S. Murphy-Arteaga received his B.Sc. degree in Physics from St.
John’s University, Minnesota, and got his M.Sc. and Ph.D. degrees from
the National Institute for Research on Astrophysics, Optics and
Electronics (INAOE), in Tonantzintla, Puebla, México. He has been a
researcher at INAOE since 1988. Since then, he has presented over 110
talks at scientific conferences, directed ten Ph.D., 18 M.Sc. and 2
B.Sc. theses, published more than 140 articles in scientific journals,
conference proceedings and newspapers, and is the author of a text book
on Electromagnetic Theory. He is currently a senior researcher with the
Microelectronics Laboratory. Dr. Murphy’s research interests are the
physics, modeling and characterization of the MOS Transistor and
passive components for high frequency applications, especially for CMOS
wireless circuits, and antenna design. He is a Senior Member of IEEE, a
Distinguished Lecturer of the Electron Devices Society, a member of the
Mexican Academy of Sciences, and a member of the Mexican National
System of Researchers (SNI).
Speaker 5: Christian Enz, EPFL (CH)
Title: Systematic
Design of Low-power Analog/RF CMOS Circuits using the Inversion
Coefficient
Abstract:
The emergence of the Internet of Things (IoT) poses stringent
requirements on the energy consumption and has hence become the primary
driver for low-power analog and RF circuit design. Implementation of
increasingly complex functions under highly constrained power and area
budgets, while circumventing the challenges posed by modern device
technologies, makes analog and RF circuit design ever more challenging.
Some guidance would therefore be invaluable for the designer to
navigate the multi-variable design space. This tutorial presents
low-power analog and RF design techniques that can be applied from
device to circuit level. It starts with the presentation of the concept
of inversion coefficient as an essential design parameter that spans
the entire range of operating points from weak via moderate to strong
inversion. Several figures-of-merit (FoM) including the and their
product, capturing the various trade-offs encountered in analog and RF
circuit design are presented. The simplicity of the base model is
emphasized and compared against measurements of 40- and 28-nm bulk CMOS
processes and BSIM6 simulations.
Bio:
Christian Enz, PhD, Swiss Federal Institute of Technology (EPFL), 1989.
He is currently Professor at EPFL, Director of the Institute of
Microengineering and head of the IC Lab. Until April 2013 he was VP at
the Swiss Center for Electronics and Microtechnology (CSEM) in
Neuchâtel, Switzerland where he was heading the Integrated and Wireless
Systems Division. Prior to joining CSEM, he was Principal Senior
Engineer at Conexant (formerly Rockwell Semiconductor Systems), Newport
Beach, CA, where he was responsible for the modeling and
characterization of MOS transistors for RF applications. His technical
interests and expertise are in the field of ultralow-power analog and
RF IC design, wireless sensor networks and semiconductor device
modeling. Together with E. Vittoz and F. Krummenacher he is the
developer of the EKV MOS transistor model. He is the author and
co-author of more than 250 scientific papers and has contributed to
numerous conference presentations and advanced engineering courses. He
is an IEEE Fellow and an individual member of the Swiss Academy of
Engineering Sciences (SATW). He has been an elected member of the IEEE
Solid-State Circuits Society (SSCS) AdCom from 2012 to 2014 and was
Chair of the IEEE SSCS Chapter of Switzerland until 2017.
Speaker 6: Humberto Andrade da Fonseca (Cadence,
US)
Title: Advanced
SOI Design and Reliability/Ageing Simulations
Abstract:
In our talk we will present 28nm FDSOI and compare this process against
conventional bulk technologies. We will then outline the design of a
high performance JESD receiver operating at 2.4Gbps with fast tracking
capability able to recover incoming data streams at over 5000ppm
offsets. We will present a novel digital phase stepping method, taking
advantage of a multi-phase ring oscillator, and the techniques to
achieve ultra low jitter in the PLL the key enablers for this
performance. Besides the advantages of FDSOI other design aspects will
be discussed with focus on mismatch, reliability analysis and aging
considerations to address the durability requirements of the harsh
automotive environment this design targeted. We will discuss the
modular implementation used to easily scale the number of receiver
lanes and how reliable and cheap at speed testing is enabled in
production together with measurement results,
Bio:
Humberto Fonseca graduated with distinction in 2002 from the University
of Porto. After a period at INESC researching FFT Algorithms, Fast
Convolution, Spread Spectrum and DSP Architectures joined Chipdea
Microelectronics’ PLL team, arising within it to the role of platform
manager and taking the responsibility to develop and consolidate
architectures for PLL and DLL based frequency and phase synthesisers
for RF and High Speed Wired Links. In 2007 after joining Texas
Instruments took the responsibility for the development of low jitter
high speed clocking components to support long reach SerDes at up to
25Gbps and later at Broadcom as Senior Principal lead the development
of the Drivers and Reader front ends for the NFC family of controllers.
In 2015 joined Cadence Design Systems to drive IP architecture in EMEA.
Humberto has written a number of articles and holds several patents in
NFC and clocking design.