MOS-AK DATE Workshop Lausanne 2017

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
Spring MOS-AK Workshop at DATE
Lausanne, March 31, 2017

Calendar

Open Directory

Books

Mission

Committee

MOS-AK: Enabling Compact Modeling R&D Exchange

Technical MOS-AK Program Promoters

Lead Sponsor

Swiss Section Sponsor

WIE Switzerland

Publishing Partner

Final MOS-AK Workshop Program

Important Dates:

Call for Papers - Dec. 2016
2nd Announcement - Jan. 2016
Final Workshop Program - Feb. 2016
MOS-AK Workshop - March 31, 2017

Venue:

Swisstech Convention Centre
Quartier Nord de l'EPFL
Route Louis-Favre 2
CH-1024 Ecublens

Agenda

Display Format:

Citation

Citation & Abstract

9:00-12:00

MOS-AK Morning Session

T_1

MOS-AK Intro
Jean-Michel Sallese and W.Grabinski
EPFL (CH), MOS-AK (EU)

T_2

ASCENT (Nanoelectronics Network) - Open Access to 14nm PDKs
Jim Greer
Tyndall National Institute (IRL)

T_3

The first stable release of Qucs-S and advances in XSPICE model synthesis
Mike Brinson*, Vadim Kuznetsov**
* Centre for Communications Technology, London Metropolitan University, UK, ** Bauman Moscow Technical University, Russia,

Abstract:
The first stable release of Qucs-S occurred simultaneous with the release of Qucs-0.0.19. Qucs-S gives access to a selection of free/open-source SPICE simulation kernels launched from the Qucs graphical user interface. This software provides a number of advanced compact modelling features, including a Verilog-A synthesizer and an on-the-fly XSPICE CodeModel synthesizer/compiler. The Verilog-A synthesizer allows Verilog-A modules to be built from Qucs subcircuits with just a single mouse click. Following, implementation of the Qucs-S Verilog-A synthesizer, the Qucs-S developers have concentrated on building XSPICE support for Qucs-S. The new modelling feature allows construction of modular compact device models suitable for circuit simulation using Ngspice and Spice Opus. With this innovative facility there is no need to recompile the whole simulator when adding a new XSPICE CodeModel. At this time, the new modelling tool is especially important, because Ngspice support for ADMS is very limited. The most challenging part of this task has been the implementation of the XSPICE CodeModel synthesizer. The paradigm of Verilog-A and XSPICE models differ significantly such that it was not found possible to convert SPICE subcircuits directly to XSPICE CodeModels. However, it has been found possible to represent Qucs EDD as an XSPICE CodeMode. Similarly, it is also possible to extract EDD parameters from Qucs equation blocks. XSPICE models require explicit definitions of model current and/or voltage partial derivatives. The Ginac GPL embedded CAS package is used by Qucs-S to find these partial derivatives as part of the overall model synthesis process. Following, successful XSPICE model synthesis Qucs-S outputs a pair of MOD and IFS files. In a similar fashion to the Qucs-S Verilog-A model synthesizer a right-click on the Qucs EDD symbol initiates the synthesis process. The XSPICE “turn-key” subsystem combined with the XSPICE model synthesizer provides a modelling tool of comparable power to the Qucs Verilog-A synthesis but designed specifically for the Ngspice and Spice Opus simulation kernels.

T_4

Interactive tool for quick calculation of design oriented MOSFET parameters
Anurag Mangla
ams AG (AT)

10:30-11:00

Coffee Break

T_5

Optimal geometry selection for Hall sensors integrated in CMOS technological process
Maria-Alexandra Paun
EPFL (CH)

T_6

Verilog-A model for ferroelectrics in organic electronics
Heinz-Olaf Müller* and Andreas Pawlak**
*Plastic Logic Germany, 01109 Dresden, Germany, **Chair for Electron Devices and Integrated Circuits, Technische Universität Dresden, 01062 Germany

T_7

Compact Modeling of the Organic TFT Devices
Benjaming Iniguez
URV (CAT)

12:00-13:00

Lunch Break

13:00-17:00

MOS-AK Afternoon Session

T_8

New Approach to Reduce Time-to-data when Characterizing Advanced Semiconductor Devices
Andrej Rumiantsev
MPI Corp. (TW)

T_9

Physics-based Modeling of Nano-Devices: Requirements and Examples
Mathieu Luisier*, Reto Rhyner**, and Aron Szabo*
*ETH Zurich (CH), **Synopsys Switzerland LLC (CH)

T_10

Semiconductor Device Compact Modelling with Ageing Effects
Felix Salfelder
University of Leeds (UK)

14:30-15:00

Coffee Break

T_11

Unified charge-based Transistor Model including Degradation Mechanisms
Theodor Hillebrand, Steffen Paul, Dagmar Peters-Drolshagen
University of Bremen (D)

T_12

Design trade-off between remote power and data communication for remotely powered sensor networks
Catherine Dehollain
EPFL, RFIC Group (CH)

T_13

Bio/Nano/CMOS interfaces for Ultrasensitive Memristive Biosensors
Sandro Carrara
EPFL (CH)

T_14

The EKV3 for Advanced Analog/RF IC Applications
Matthias Bucher
TUC (GR)

17:00

End of the MOS-AK Workshop

Extended MOS-AK Committee:

Committee

Local MOS-AK Organization Chair

Jean-Michel Sallese, EPFL (CH)

MOS-AK Workshop Manager

Wladek Grabinski, MOS-AK (EU)

International MOS-AK Board of R&D Advisers

Larry Nagel, Omega Enterprises Consulting (USA)
Andrei Vladimirescu, UCB (USA); ISEP (FR)

Technical Program Committee
MOS-AK North America
Chair: Pekka Ojala, Exar Corporation
Co-Chair: Geoffrey Coram, Analog Devices
Co-Chair: Prof. Jamal Deen, U.McMaster
Co-Chair: Roberto Tinti, Keysight EEsof Division
MOS-AK South America
Chair: Prof. Gilson I Wirth; UFRGS; Brazil
Co-Chair: Prof. Carlos Galup-Montoro, UFSC; Brazil
Co-Chair: Sergio Bampi, UFRGS, Brazil
Co-Chair: Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
MOS-AK Europe
Chair: Ehrenfried Seebacher, AMS, Austria
Co-Chair: Alexander Petr, XFab, Germany
Co-Chair: Prof. Benjamin Iniguez, URV, Spain
Co-Chair: Franz Sischka, SisConsult, Germany
MOS-AK Asia/South Pacific
Chair: Sadayuki Yoshitomi, Toshiba (J)
Co-Chair: Min Zhang, XMOD Technologies, (CN)
Co-Chair: Xing Zhou, NTU Singapore (SG)
Co-Chair: A.B. Bhattacharyya, JIIT New Delhi (IN)

No.#12100

update: Feb. 2017 (rev. f)