Important Date: |
- Call for Papers - March
2023
- 2nd Announcement - May
2023
- Final Workshop Program -
Aug. 2023
- MOS-AK Workshop in
Lisbon - Sept.11 2023
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Venue:
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Lisboa
Congress Centre - CCL |
Online |
Registration (as of Aug. 2023) any related enquiries can be sent to registration@mos-ak.org |
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Synopsis and Workshop Topics
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Synopsis: |
- HiTech
forum to discuss the frontiers of electron device modeling with
emphasis on simulation-aware compact/ SPICE models and its Verilog-A
standardization. Together with local host, as well as all the Extended MOS-AK TPC Committee,
would like to invite you to the 20th subsequent MOS-AK Workshop at ESSDERC/ESSDERC
in Lisbon.
- MOS-AK
Meetings are organized with aims to strengthen a network and discussion
forum among experts in the field, enhance open platform for information
exchange related to compact/Spice modeling and Verilog-A
standardization, bring people in the compact modeling field together,
as well as obtain feedback from technology developers, circuit
designers, and CAD tool vendors. The topics cover all important aspects
of compact model development, implementation, deployment and
standardization within the main theme - frontiers of the compact
modeling for nm-scale MEMS/NEMS designs, CMOS/SOI and HEMT IC
simulation.
- The
specific workshop goal will be to classify the most important
directions for the future development of the electron device models,
not limiting the discussion to compact models, but including physical,
analytical and numerical models, to clearly identify areas that need
further research and possible contact points between the different
modeling domains. This workshop is designed for device process
engineers (CMOS, SOI, BiCMOS, SiGe, GaN, InP) who are interested in
device modeling; ICs designers (RF/Analog/Mixed-Signal/SoC/Bio/Med) and
those starting in that area as well as device characterization,
modeling and parameter extraction engineers. The content will be
beneficial for anyone who needs to learn what is really behind the IC
simulation in modern device models in particular using free open source
PDKs.
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Topics |
to be covered include the
following among other related to the compact/SPICE modeling and its
Verilog-A standardization:
- Compact Modeling (CM) of the electron devices
- Advances in semiconductor technologies and processing
- Verilog-A language for CM standardization
- New CM techniques and extraction software
- Open Source (FOSS) TCAD/EDA modeling and simulation
- CM of passive, active, sensors and actuators
- Emerging Devices, Organic TFT, CMOS and SOI-based
memory
- Microwave, RF device modeling, high voltage device
modeling
- Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and
circuits
- Technology R&D, DFY, DFT and
reliability/aging IC designs
- Foundry/Fabless Interface Strategies (eg: free PDKs:
Skywater, GF, IHP)
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Coordinators: | - Antonio L. Topa, Universitario de Santiago (P)
- Rafael Ferreira da Silva Caldeirinha, Instituto Politecnico de Leiria (P)
- Pedro Pinho, Universidade de Aveiro (P)
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Moderator | - Wladek Grabinski, MOS-AK (EU)
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Speakers | tentative MOS-AK panelists' list (alphabetic order)
- Sheikh Aamir Ahsan, NITSRI (IN)
- Maria Helena Fino, UNL (P)
- Rene Scholz, IHP (D)
- Abby Shih, Keysight (US)
- Daniel Tomaszewski, IMiF, Warsaw (PL)
- Sadayuki Yoshitomi, GigaChip (J)
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