London Metropolitan University
Graduate Centre
166-220 Holloway Road
London N7 8DB

Abstract: 
Increased miniaturisation and integration of next generation of wireless systems is a major challenge as a typical RF and microwave communications system comprises of individual electronic modules such as the synthesised sources, mixers and amplifiers interconnected by couplers, filters and transmission lines which guide the signal to and from the antenna. Although recent devices and design techniques have led to improvements in the performance of the communications transceiver, however the overall size and topology have remained unchanged. The fundamental problem is that components such as filters, couplers and antennas have dimensions that are fixed to the wavelength of the signal. This is the critical design issue which not only precludes size reduction and integration it also limits the system bandwidth. The research work at London Met is focused on providing a solution to this problem by using the phenomenon of metamaterial to substantially reduce the physical size of wavelength dependent components that hinder the miniaturization of RF and microwave systems. Metamaterials are artificial homogeneous electromagnetic structures with unusual properties not readily found in nature, namely exhibiting a double negative permittivity and permeability. They owe their effective electromagnetic response to the sub-wavelength dimension of their average unit cell constituting the structure. This technology has generated vast amounts of research and development recently, and their scientific and technological potential is far from being exhausted. The presentation will review the techniques to develop and model structures that exhibit metamaterial characteristics. Experimental evidence will be provided to demonstrate the practicality of implementing microwave components using the metamaterial phenomenon, as well as the advantages afforded by this technology.

Abstract: 
Ultrathin silicon chips with a thickness down to 10um are highly flexible. They can be integrated into foil based thin packages. Such a microsystem can be bended like a sheet of paper without losing its functionality. However, the deformation causes mechanical stress in the silicon which influences the electrical behavior of MOS transistors on this chip. As this is mostly seen as an unwanted parasitic effect, it can be used as well in a positive sense to detect bending with respect to strength and orientation. To design sensor circuits based on this principle, a simulation model covering the effects of mechanical stress is required. This paper describes how a standard PSP 103 model was enhanced by integrating the necessary code into the open Verilog-A code of the model. The extraction of model parameters required dedicated measurements on both stressed and unstressed devices. Finally, the model was applied to develop a sensor chip that demonstrates the feasibility of this technology for such an application. The sensor chip also acts as a verification vehicle for the simulation model itself.

Abstract: 
The EPFL-JL v1.0 is a physics-based compact model for junctionless symmetric double gate MOSFETs relying on a charge-based approach. The model is valid in all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation, and still doesn't need for any fitting parameters. The model has been implemented as sub-circuits and is compatible for Hspice simulations for n and p-channel junctionless Double Gate as well as for nanowire FETs architectures. In addition, the model also accounts for the intrinsic capacitance network which is required for accurate time dependent simulations of digital and analog circuits. Finally, the proposed implementation can also be imported as a library in Cadence virtuoso or Advanced Design System (ADS).

Abstract: 
In this paper a gradual investigation of a particular Hall sensor in SOI (“Silicon-On-Insulator”) technology is presented. The most important parameters of a specific Hall cell, based on SOI structure, are evaluated through three-dimensional physical simulations. The fact that the depth of the active silicon layer in SOI integration process is much smaller than in a regular CMOS is immediately reflected in both increased sensitivity and increased input resistance. The Hall shape is modeled after an XFAB SOI XI10 integration process. The magnetic sensors in this particular non-fully depleted SOI technology are highly suitable for high temperature applications. In order to verify its behaviour, the Hall voltage and absolute sensitivity were obtained through simulations. The temperature influence was also investigated for the considered SOI Hall cell. A comparison between the performance of the same Hall cell in both regular bulk and SOI CMOS technology is also made. The results obtained are in accordance with the literature.