Abstract: 
MOS-AK is HiTech forum to discuss the frontiers of electron device modeling with emphasis on simulation-aware compact/SPICE models and its Verilog-A standardization. The specific workshop goal will be to classify the most important directions for the future development of the electron device models, not limiting the discussion to compact models, but including physical, analytical and numerical models, to clearly identify areas that need further research and possible contact points between the different modeling domains. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe, GaN, InP) who are interested in device modeling; ICs designers (RF/Analog/Mixed-Signal/SoC/Bio/Med) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind the IC simulation in modern device models.

Abstract: 
High efficiency modes such as continuum modes rely on the harmonic manipulation of the waveforms in power amplifiers to improve efficiency, output power and robustness against impedance mismatch. Their design benefits from accurate modelling of capacitances in the knee region of the transistor, which may not be easy to extract from measurement due to noise and uncertainty. A table-based model typically has to rely on interpolation and extrapolation for such bias points to ensure a continuous and differentiable behaviour. In this work, we propose a polynomial-based model which satisfies charge conservation at the gate terminal. This model can be used directly for Volterra based analysis to quantify the distortion from capacitors and to find cancellation mechanisms for the feedback capacitance, which is a problem especially for CMOS based amplifiers in 5G applications.

Abstract: 
MOSFET mismatch measurements and characterization are repetitive tasks that require a huge amount of measurements, testing time, and data post-processing. In this presentation, an array test structure and a measurement method are proposed. They extraordinarily improve mismatch measurement time with a reduced equipment setup, while maintaining a high statistical confidence level. The structure is based on the combination of two stacked MOS transistors and the measurement methodology relies on just two single DC voltage measurements. With a theoretical speed improvement of 30x, the method enables fast extraction of MOSFET mismatch parameters, useful to designers, such as AVTH and Aβ with less than 2% error. The data correlation coefficient between the traditional and the proposed method is not less than 0.94, obtained in bulk CMOS test chips, thus confirming the high statistical confidence of the extraction method.

Abstract: 
Compact modeling of CMOS devices has advanced day by day in the last few decades, keeping abreast with the technological development of manufacturing processes with ever smaller minimum features. These advances have made it possible to design and built circuits for operation in high frequencies, reaching into the hundreds of GHz. Notwithstanding, as the frequency of operation increases, several second-order effects become apparent, and it is important to consider them at the design table in order to obtain more reliable simulations. Some of these have to do with parasitic effects of the interconnect lines; effects associated with inductors; connectors; and the like. Furthermore, higher operating frequencies make it possible to include antennas on-chip for a host of applications, but compact modeles for these have not been satisfactorily developed. This talk aims at presenting some of these considerations raising awareness of their importance in the modeling of RF CMOS circuits.

Abstract: 
Compared to graphene, TMD materials offer the advantage of having the semiconductor properties which allow them to be used as essential components in logic integrated circuits. The small thickness for TMD semiconductors enables the ultimate scalability in FETs, due to a higher gate electrostatic controllability over the channel. To use those new devices in VLSI circuits, compact design-oriented models need to be developed. We review the physics of different structures of TMD FETs and aproaches to develop analytical equations of the I-V and C-V characteristics

Abstract: 
Nanowire and Nanosheet MOSFET devices also require precise analytical models that can be used in circuit simulators. In this presentation, we demonstrate that the Symmetric Doped Double-Gate Model (SDDGM) can be used for modelling Nanowires and Nanosheets, due to the specific characteristics of these structures and of the model SDDGM. In this paper, 3D TCAD simulations are used to confirm that the total channel width for these structures is equal to the perimeter of the transistor sheet, allowing to extend of the application of the Symmetric Doped Double-Gate Model (SDDGM) model to Nanowires and Nanosheets MOSFETs, with no need to include new parameters. The Model SDDGM is validated for this application using several measured and simulated structures of Nanowires and Nanosheets transistors, with different aspect ratios of fin width and fin height, showing very good agreement between measured or simulated characteristics and modelled. SDDGM is encoded in Verilog-A language and implemented in the SmartSPICE circuit simulator.

Abstract: 
Charge trapping produces Random Telegraph Noise (RTN - time domain), 1/f Noise (frequency domain) and Bias Temperature Instability (BTI - aging). A statistical compact modeling framework, based on discrete device physics quantities, is presented. Parameter extraction is addressed, showing that parameters extracted in frequency domain may be used to address time domain behavior, and vice-versa. Not only expected average behavior is addressed, but also the variability, enabling statistical analysis, including corner-based analysis. Electrical (SPICE) level simulation techniques are discussed.