Arbeitskreis MOS-Modelle und Parameterextraktion MOS Modeling and Parameter Extraction Working Group MOS-AK/GSA ESSDERC/ESSCIRC Workshop Sept.17, 2010  Seville

MOS-AK 2010: Over Two Decades of Enabling Compact Modeling R&D Exchange

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MOS-AK/GSA Workshop Program

Venue:	Barceló Renacimiento Hotel Seville (driving directions)
Agenda:	Sept. 17, 2010 MOS-AK/GSA ESSDERC/ESSCIRC Workshop "Frontiers of the Compact Modeling for Advanced Analog/RF Applications"
Display Format: Citation Citation & Abstract
9:00	Morning Session - Chair: Dr. H. Jaouen; STM
T_1	Modeling Standardization: Enabling the worldwide design community Josef Watts IBM, Compact Modeling Council (USA) Abstract:  The number of organizations developing semiconductor processes continues to decrease, driven by the high cost of process development and the high production volumes required for a fabricator to be economically viable. This means that geographically and organizationally most circuit designers are far removed from the foundry who will fabricate their designs. The compact model council is key player in the process of enabling circuit designers around the world to develop products with confidence that their designs will work when fabricated. This talk will describe the rigorous process by which a model becomes a standard,report on the current state of standard compact models and preview future trends, including: Why and how Verilog-A is becoming the standard language of compact models; An industry standard API for efficiently customizing compact models; A standard spice language robust enough to specify a PDK once for all simulators; A standard approach to specifying process variation.
T_2	Advances in Multigate MOSFET Modeling Benjamin Iniguez URV (ES) Abstract:  tbd
10:00 - 10:30	Coffee Break
T_3	SMASH: a Verilog-A simulator for analog designers Gilles Depeyrot, Frédéric Poullet and Benoit Dumas Dolphin Integration (F) Abstract:  With the SPICE compatibility extensions of the Verilog-AMS Language Reference Manual, Verilog-A has the potential to revolutionize the paradigm of analog design of integrated circuits and totally replace SPICE. The achievement of this goal depends on the adoption of Verilog-A by all concerned actors: EDA vendors, compact model developers, semiconductor foundries as well as final users. However, both final users and semiconductor foundries cannot accept degradation in simulation speed, memory consumption, or loss of functionalities. Based on the previously presented and published Verilog-A Compact Model Coding Guidelines, this presentation will take stock on the evolutions of SMASH during the recent years to make the Verilog-A simulator as competitive as the SPICE one in the context of analog design.
T_4	Progress in Applying On-Wafer Calibration Techniques for Advanced High-Speed Silicon Technologies Andrej Rumiantsev*$, Franck Pourchon** *Cascade Microtech Dresden GmbH, **STMicroelectronics, $CEDIC, Dresden University of Technology (D) Abstract:  On-wafer RF calibration methods are compared to the conventional Impedance Standard Substrate (ISS) calibration combined with dummies de-embedding approach for transistors of an advanced silicon process. We discuss the design of customized calibration standards, addressing specifics of the silicon process. Our results show that on-wafer calibration methods are the most suitable approaches for accurate characterization of sub-THz transistors.
11:30-12:00	Poster Session
12:00-13:30	Lunch
13:30	Afternoon Session - Chair: Prof. A. Vladimirescu; UC Berkeley
T_5	Challenges in Modeling Layout Systematic Effects in Compact Device Models Andrzej J. Strojwas PDF Solutions (USA) Abstract:  tbd
T_6	Recent Developments in Device Reliability Modeling Tibor Grasser TU Wien (A) Abstract:  Many reliability issues in modern CMOS devices like the bias temperature instability, hot carrier degradation, stress-induced leakage currents, random telegraph and 1/f noise are linked to the injection of charge into the insulating layer. Charge injection models will be discussed starting from the conventional elastic tunneling process to more realistic nonradiative multiphonon processes. In addition, evidence will be presented which demonstrates that charge trapping creates annealable defects inside the oxide. Prior annealing, these defects can change their charge state by following the position of the Fermi-level inside the channel. As a consequence, these defects can temporarily contribute to random telegraph and 1/f noise. Of particular importance is that these charge capture processes are often reversible, with widely distributed timescales. For instance, degradation introduced by a negative bias temperature stress recovers linearly on a logarithmic timescale starting from the microsecond regime and continues for weeks. Conventional reliability models cannot properly account for this recovery effect, which is, however, indispensable in order to explain for instance the differences between DC and AC stress. Without consideration of recovery, predicted lifetimes will be wrong by orders of magnitude. A simple RC-equivalent model will be discussed which accurately captures this phenomenon.
T_7	Compact modeling of nanoscale MOSFETs: beyond the drift diffusion approximation Raphael Clerc IMEP, MINATEC (F) Abstract:  The quasi ballistic nature of transport in end of the roadmap MOSFETs devices is expected to lead to significant on state current enhancement. As the consequence, this regime of transport has been extensively investigated in the last 15 years, in the field of device simulation as well as device compact modeling. In this talk, the current understanding of quasi ballistic transport will be reviewed and discussed, focusing on the consequences of these researches on the area of compact modeling. In addition, different strategies to compare these models to experimental data will be briefly discussed, addressing the difficulties to estimate the “degree of ballisticity” achieved in advanced technologies.
15:30 - 16:00
T_8	Surface potential amplification model of the negative capacitance FET David Jiménez, Enrique Miranda and Andrés Godoy UAB (ES), UAB (ES), UGR (ES) Abstract:  It has been proposed that a ferroelectric material operating in the negative capacitance region could act as a step-up converter of the surface potential in a metalferroelectric-semiconductor structure, opening a new route for the realization of transistors with steeper subthreshold characteristics (S<60 mV/decade). In this presentation, a comprehensive physics-based surface potential model for the negative capacitance field-effect transistor is reported. The model is aimed to evaluate the surface potential amplification capability. Moreover this work clarifies how can experimentally be detected operation in the negative capacitance region of the ferroelectric.
T_9	The EKV/ACM compact models for mismatch modeling down to 90nm and for new emergent non-CMOS nanotechnology FETs Teresa Serrano-Gotarredona and Bernabé Linares-Barranco IMSE-CNM-CSIC (Instituto de Microelectrónica de Sevilla) (ES) Abstract:  We present the use of the EKV/ACM compact and continuous from weak-to-strong inversion model for modeling CMOS mismatch transistor mismatch down to 90nm, validated by experimental characterizations. The basic model is adapted to include some second order effects critical for mismatch. At the end view show a possible way of exploiting these models to characterize a new set of non-CMOS nano scale FET devices such as Carbon Nano Tube FETs, organic FETs, and ZnO nano wire FETs.
17:00	Workshp Closing
Committees:	Local Organizing Committee: Andres Godoy, UGR Benjamin Inigues, URV Rodrigo Picos, UIB Extended MOS-AK/GSA Committee: Lisa Tafoya, Vice President, Global Semiconductor Alliance (GSA) Chelsea Boone GSA; Senior Research Analyst Wladek Grabinski, GMC Suisse; MOS-AK/GSA Group Manager MOS-AK/GSA North America: Chair: Pekka Ojala, Exar Corporation Co-Chair: Geoffrey Coram, Analog Devices Co-Chair: Prof. Jamal Deen, U.McMaster MOS-AK/GSA South America: Chair: Prof. Gilson I Wirth; UFRGS; Brazil Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil MOS-AK/GSA Europe: Chair: Ehrenfried Seebacher, austriamicrosystems AG Co-Chair: Sebastian Schmidt, XFab Co-Chair: Prof. Benjamin Iniguez, URV MOS-AK/GSA Asia/Pacific: Chair: Goichi Yokomizo, STARC, Japan Co-Chair: Sadayuki Yoshitomi, Toshiba, Japan Co-Chair: Xing Zhou, NTU, Singapore

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update: Sept. 2010 (rev. F)

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