MOS-AK: 20 Years of Enabling Compact Modeling R&D Exchange 
Arbeitskreis MOS-Modelle und Parameterextraktion
MOS Modeling and Parameter Extraction Working Group
1st International MOS-AK Meeting
(co-located with the CMC Meeting and IEDM Conference)
Agenda: Saturday, 13 December 2008; The Westin St Francis Hotel in San Francisco
  • Morning Session
    • 9:00-12:00 Oral presentations
    • 10:00-10:30 (coffee break)
  • 12:00-13:00 Lunch
  • Afternoon Session
    • 13:00-16:00 Oral presentations
    • 14:30-15:00 (coffee break)
  • Panel Session
 MOS-AK Meeting Sponsors
Accelicon
sponsor lead
SUSS MicroTec
Technical Program Promoters
EuroTraining GSA 
ijnm_wiley COMON EC Project
MOS-AK Meeting Program
Display Format: Citation Citation & Abstract
9:00 Workshop Opening: Wladek Grabinski 
9:00-11:45 Morning Session - Chair: Hisayo S. Momose; Toshiba
  Verilog-A is for Equation Specification, not for Modeling
Colin McAndrew1, Laurent Lemaitre1, Zoltan Huszka2, and Geoffrey Coram3; 1Freescale, 2AMS, 3Analog Devices
  Developing and releasing compact models using Verilog-A
Marek Mierzwinski, Patrick O'Halloran, and Boris Troyanovsky; Tiburon Design Automation Santa Rosa, CA
  PSP Family of Compact Models - Overview and recent developments
G. Gildenblat, W. Wu, X. Li, Z. Zhu, W. Yao, Q. Zhou, A. Dey and D. Gajanan (ASU)
G.D.J. Smit, A. Scholten and D.B.M. Klaassen (NXP)
  Modeling of Metal Gate / High-k MOSFET Devices with PSP
Joachim Assenmacher; Infineon Technologies and Jae-Eun Park, IBM 
  A complete stress modeling solution for 32nm technology and beyond
Albert Yanfeng Li1, Xisheng Zhang1, Riko Radojcic2, 1Accelicon Technologies, 2Qualcomm
11:45-12:00 Late News Posters - Chair: Wladek Grabinski; GMC Suisse 
12:00-13:00 Lunch
13:00-16:00 Afternoon Session - Chair: Sebastian Schmidt; XFab
  The HiSIM family of compact models for integrated devices
H. J. Mattausch, N. Sadachika, M. Miyake, H. Kikuchihara, U. Feldmann, and M. Miura-Mattausch; Hiroshima University
  Asymmetric Double Gate MOSFET Compact Model
Henok Abebe1, Ellis Cumberbatch2, Hedley Morris2 and Vance Tyree1; 1University of Southern California, 2Claremont Graduate University
  Sizing analog MOS circuits by means of the gm/ID methodology and a compact model
Paul Jespers; UC Louvain  
  A Practical Guide to Accurate Broadband On-Wafer Calibration for RF Silicon Applications
Andrej Rumiantsev; SUSS MicroTec
  Using Large-Signal Measurements for Transistor Characterization and Model Verification in a Device Modeling Program
Maciej Myslinski1, Giovanni Crupi2, Marc Vanden Bossche3, Dominique Schreurs1, and Bart Nauwelaers1; 1Katholieke Universiteit Leuven, Belgium, 2University of Messina, Italy, 3NMDG N.V.
16:00-17:00 Panel Session - Chair: Ehrenfried Seebacher; austriamicrosystems

Contributors:
Al Kordesch; Silterra
Paolo Nenzi; Uni Roma; slides
Sebastian Schmidt; XFab
Joe Watts; IBM; slides
after 17:00  Post MOS-AK Reception

Art Gallery NOMA
80 Maiden Lane
San Francisco
www.nomagallerysf.com
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No.#16380
update: 31-Dec-08 (rev.g)
Contents subject to change 1999-2008 All rights reserved. WG
Graphics 2008 Oliver