 Wladek
Grabinski received the Ph.D. degree from the Institute of Electron
Technology, Warsaw, Poland, in 1991. From
1991
to 1998 he was a Research Assistant at the
Integrated Systems Lab, ETHZ, Switzerland, supporting the CMOS and
BiCMOS technology developments by electrical characterization of the
processes and devices. From 1999 to 2000, he was with LEG, EPFL, and
was engaged in the compact MOSFET model developments supporting
numerical device simulation and parameter extraction. Later, he was a
technical staff engineer at Motorola, and subsequently at Freescale
Semiconductor, Geneva Modeling Center, Switzerland. He is now a
consultant responsible for SPICE modeling, characterization and
parameter extraction of MOST devices for the analog/RF IC applications.
He is currently consulting on the development of next- generation
compact models for the nanoscaled technology very large scale
integration (VLSI) circuit simulation. His current research interests
are in high-frequency characterization, compact modeling and its
Verilog-A standardization as well as device numerical simulations of
MOSFETs for analog/RF low power IC applications. He is an editor of the
reference modeling book Transistor Level Modeling for Analog/RF IC
Design and also authored or coauthored more than 50 papers. Wladek is
the chair of the ESSDERC Track4: "Device and Circuit Compact Modeling"
as well as has served as a member of organization committee of
ESSDERC/ESSDERC, TPC of SBMicro, SISPAD, MIXDES Conferences; reviewer
of the IEEE TED, IEEE MWCL, IJNM, MEE, MEJ. He is a Member At Large of
Swiss IEEE ExCom and also supports the EPFL IEEE Student Branch acting
as its Interim Branch Mentor. Wladek is involved in activities of the
MOS-AK Association and serves as a coordinating manager since 1999.
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