Abstract: 
The specific workshop goal will be to classify the most important directions for the future development of the electron device models, not limiting the discussion to compact models, but including physical, analytical and numerical models, to clearly identify areas that need further research and possible contact points between the different modeling domains. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe, GaN, InP) who are interested in device modeling; ICs designers (RF/Analog/Mixed-Signal/SoC/Bio/Med) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind the IC simulation in modern device models in particular using free open source PDKs.

Abstract: 
Benchmarking metrics for circuits based on Field Effect Transistors are discussed. The basics mechanisms involved in charge trapping are presented. Modeling techniques to abstract the physical level effects into the circuits design flow are studied. Charge trapping leads to noise and aging (BTI). Noise levels and BTI degradation can vary by several orders of magnitude in deeply scaled devices, making variability a major concern in advanced MOS technologies. Therefore, to assure proper circuit design in this scenario, it is necessary to identify the fundamental mechanisms responsible for variability of noise and BTI. The applicability of the model here presented to the evaluation of integrated circuits in both time and frequency domain is discussed.

Abstract: 
In this talk, the characteristic impedance (Zc) extraction from experimental data is explored. Different problems in the Zc vs frequency (f) curves (associated with the adapters used to access the lines) are exposed, such as a different level of Zc with respect to the expected value, and resonances due not only to signal reflections in the transmission line structure, but also along the adapter length. Ad hoc structures were used to analyze the effects of connectors, needed to probe transmission lines, both on- chip and on printed circuit boards (PCBs).

Abstract: 
The current scaling of MOSFETs towards sub-20 nm long devices is being sustained by adopting devices using multiple gate (MuGFETs) architectures. Amongst the MuGFETs, the FinFETs achieved maturity for mass production. FinFETs are made with tall and narrow silicon fins. For the scaling of FinFETs, nanowire MOS transistors (or simply nanowire transistors) emerged as an excellent alternative. Nanowire transistors are FinFET-like structures consisting of three gates, with the transistor Fin height (HFIN) having a similar dimension as Fin width (WFIN). If the device has a WFIN wider than HFIN and the gate surrounds the silicon region this transistor is referred as nanosheet transistor. When more than one transistor is placed over other, a stacked structure is obtained. Recently, a compact model developed for FinFETs, the Symmetric Doped Double-Gate Model (SDDGM) was complemented and validated for modelling the drain current of nanowire and nanosheet transistors. However, the modelling of nanowires, nanosheet and stacked MOS devices at high temperatures was missing. Recently, we analysed the possibility of using the expressions in the SDDGM, that include all temperature-dependent factors, for modelling nanowire, nanosheets and staked MOS devices with temperature. Additionally, the leakage current as function of temperature was analysed for nanowires, which include the tunnelling currents and an additional current component of P-N junction Source-Channel, that was not previously considered. The drain current, considering the above-mentioned leakage currents, is then calculated as function of temperature. In this presentation, we show the modelling of nanowires, nanosheet and stacked MOS with temperature. The modelling of nanowires, including all components of the leakage current, also as function of temperature, is also presented. All results are validated with experiment.

Abstract: 
We discuss a model for HEMT that inherits from the concepts of charge linearization and normalization of electrical quantities enabling a simple and design-oriented analytical model. We show that such a model shares many similarities with regular MOSFETs, and in particular the EKV model, even though the roots are very different. In particular, we introduce the notion of Inversion Coefficient which can be used in place of the gate voltage when the transistor operates in saturation. Additionally, this gives the transconductance-to-current ratio gm/ID a simple expression that can also be used to identify unambiguously the regime of operation of HEMTs.

Abstract: 
The design of TMD (Transition Metal Dichalcogenide) memristor synapses, requires accurate analytical and compact models for these devices. A number of compact models for memristors based on different materials have been presented, but very little work has been carried out to model TMD memristors. A comprehensive analysis of the physical mechanisms which determine the behavior of TMD memristors is still missing. In this lecture we review the main physical phenomena which can affect the behavior of TMD memristors and we present possible solutions to model these phenomena and incorporate them to a compact device model. Recently some progress has been done Ab initio simulations provided some insights in the physical mechanisms of the switching process of MoS2 memristors. Two types of dc-programmes switching modes were identified in lateral MoS2 memristors In addition, models of electrochemical metallization-based transport in vertical TMD memristors have recently been presented We will also discuss how we could adapt to TMD memristors several compact models developed for memristors based on other materials.

Abstract: 
The world is facing critical moments, in one hand the production of food is negatively impacting the climate change, as it responsible of almost 1/3 of the GHG emissions even though agriculture is one of the most impacted sectors by climate change. On the other hand, the world needs more food. FAO from United Nations is estimating the agricultural production needs to be increased by 70% by 2050, and it has to be sustainable. The dilemma is then how to increase the food production in a sustainable way. Electronics and technology can be part of the solution to this dilemma. In this talk we will present the impact of climate change in agriculture, the impact of agriculture in climate change, and how electronics and technology are part of the solution presenting some challenges and how they are being addressed.

Abstract: 
The noise performance of most analog circuits can be accurately extracted from cheap simulations in the frequency domain. However, for circuit operating in large-signal conditions and/or exhibiting substantial nonlinearities, transient noise analyses are required. We will review the tool offered by industrial SPICE simulators such as Eldo® from Siemens EDA® or Virtuoso® Spectre® from Cadence®. The generation of random Gaussian noise sources in the time domain according to the compact model of the simulated devices will be addressed, as well as the incorporation of the random telegraph noise. In the light of recently published results from stochastic thermodynamics, we will also discuss the relevance of the Gaussian model universally used for the thermal noise, both from the point of view of thermodynamic consistency and from a circuit design perspective. Finally, we will present a few cases of noise-induced transient bit flips in ultra-low-voltage SRAM bitcells, as an application of the simulation methodology.