Map

The hotels at the link below have an agreement with "La Sapienza";
http://www.uniroma1.it/organizzazione/postaeservizi/servizipersonale/risorse/default.php
Hotel Palatino http://www.hotelpalatino.com/

Best Western Hotel Globus Rome http://www.globushotelrome.it/
Hotel Felice in San Lorenzo area http://www.hotelfelice.com/en/home.html
Hotel Laurentia http://www.hotellaurentia.com/index.php

Abstract: 
Stress induced voiding (SIV) represents one of the main sources of the reliability issues in ULSI circuits back-end of line (BEOL). SIV consists in the break of a metal line or a via hole occurring in absence of a current flow and, up to date, there is not a unanimously accepted theory of the SIV phenomenon. This article provides a theoretical analysis of the mechanisms inducing voiding in aluminium via-holes in a bridge in the BEOL of a real CMOS production process and attempts a model of SIV. In such real structures, TEM observations systematically put in evidence that the fracture of the void started from mid-height approximately. Finite element simulations (FES) have been performed to derive the mechanical stress profile in the examined structures, using the mono-axial tension (or equivalent tensile stress) of Von Mises. FES showed that, due to the particular geometry of the structure and to the used materials, the maximum of the stress occurred close to mid-height of the via. This makes that location a preferential site for void nucleation and leads to a low activation energy for the void formation. Once a void is nucleated, it can grow due to vacancies diffusion and clustering. The diffusion of vacancies is driven by the stress gradient and is maximal toward the center of the via and along its side-walls, giving rise to the void geometry observed with TEM. Alternative structures, designed with different geometries or materials were investigated, with the aim of providing a design tool for future nodes.

Abstract: 
We present a compact, semi-empirical model of CNTFETs, in which we propose several issues to allow an easy implementation in the most common circuit simulators, such as SPICE. The model is based on the hypothesis of fully ballistic transport in a mesoscopic system and on analytical approximations, introduced to avoid the resort to self-consistency. The CNTFET equivalent circuit is similar to a common MOSFET one, in which we have numerically determined the flat band voltage and the resistances of the doped regions by a best-fit procedure between the measured and simulated values of output device characteristics, while the quantum capacitances have to be computed from the charge in the channel. To verify the accuracy of the proposed model, the results have been compared with those of the numerical model online available and of experimental data, with a negligible relative error in both cases (less than 5%). Moreover the good agreement between simulation and experimental results for a p-type CNTFET demonstrates the validity of proposed model, born for a n-type CNTFET, also for this kind of devices. Finally we apply the model in the SPICE simulator to design some electronic circuits, demonstrating the importance of the quantum capacitance dependence on polarization voltages and investigating about the effects of the CNT quantum resistances and inductances.

Abstract: 
The first two-year results of the European Research Project CATHERINE (http://www.catherineproject.eu) have demonstrated that a certain degree of control of the morphology and properties of multi-wall carbon nanotubes (MWCNTs) for nanointerconnect applications can be achieved through a suitable fabrication process that make use of a porous alumina membrane for the self-assempling of multiwall carbon nanotubes (MWCNTs) with desired characteristics. However, one of the main limitation of this approach is still the compatibility with CMOS process. Recently, it has been noted that graphene has the potential for circumventing many of the integration challenges that face CNT technology for fabricating high mobility planar devices. One of the main limitations in the practical use of graphene in nano-components is the capability of full control of the functional properties in relationship with the structural characteristics and morphological nano-scale. To this purpose, multiscale multiphysics and reliability properties simulation tools should be developed. Moreover, radio-frequency (RF) and microwave (MW) simulation models for high-frequency operation prediction are needed for graphene-based device design and future integration in high-density packages. Currently, such models are widely available for CNT-based devices, like nanointerconnects. The scope of this paper is to present compact models for the signal propagation and signal integrity analysis at radio frequency (RD) of nanointerconnects made either of MWCNTs or multilayer graphene nanoribbons (GNRs).