Arbeitskreis MOS-Modelle und Parameterextraktion
MOS Modeling and Parameter Extraction Working Group
5th International MOS-AK/GSA Workshop
(co-located with the CMC Meeting and IEDM Conference)
San Francisco Dec.12, 2012
MOS-AK 2012: Over Two Decades of Enabling Compact Modeling R&D Exchange
  MOS-AK/GSA Workshop Sponsors
Agilent
 Mentor Graphics
  Technical MOS-AK/GSA Program Promoters
GSA COMON EC Project EuroTraining MOSIS
The MOSIS Services

Technical MOS-AK Program
Venue: SwissNex SFswissnex San Francisco
730 Montgomery Street
San Francisco, CA 94111, USA
Important Dates:
  • Preannouncement - Sept. 2012
  • Call for Papers - Oct. 2012
  • Final Workshop Program - Nov. 2012
  • MOS-AK/GSA Workshop - Dec. 12, 2012 (9:00am - 5:00pm)
    • 9:00am - 12:00 Morning Session
    • 1:00pm - 4:00pm Afternoon Session
    • 4:00pm - 5:00pm Panel: Status and Future of Verilog-A Compact Modeling Standardization
      • Moderator: Larry Nagel
    • 5:00pm End of the MOS-AK/GSA workshop
Agenda:  
Display Format: Citation Citation & Abstract
9:00-12:00
 Morning Session (Chair: Wladek Grabinski, MOS-AK)

Welcome and workshop opening
Harrison Beasley, GSA and Wladek Grabinski, MOS-AK
T_1  Scaling Challenges of Analog Electronics
Mustafa Badaroglu
IMEC (B)
T_2  i-MOS: an interactive Modeling and Online Simulation Platform
 Hao Wang and Mansun Chan
HKUST (HK)
T_3  Nonlinear Device Modeling with Scalable X-parameters
 David E. Root, Mihai Marcu, Jason Horn, Jianjun Xu, Radek M. Biernacki, and Masaya Iwamoto
Agilent Technologies (US)

Coffee Break
T_4 PSP model update
 Gert-Jan Smit, Andries Scholten, D.B.M. Klaassen and Ramses van der Toorn*
NXP Semiconductors, *Delft University (NL)
T_5
 KLU and PSS implementations in NGSPICE
 Francesco Lannutti and Stefano Perticaroli
Sapienza University of Rome (I)
T_6 GCC front-end of Compact Modeling Verilog-AMS language
 Laurent Lemaitre
noovela (F)
12:00-13:00
 Lunch
13:00-16:00
 Afternoon Session (Chair: Ehrenfried Seebacher, AMS)
T_7 Global Geometrical Scaling in BSIM6
 Y. S. Chauhan*,**, M. Chalkiadaki***, S. Venugopalan**, M. A. Karim**, N. Paydavosi**, S. Jandhyala**, J. P. Duarte**, C. C. Enz***, A. M. Niknejad**, C. Hu**
IIT Kanpur (IN), UC Berkeley (US), EPFL (CH)
T_8
 SPICE Modeling of STT-RAM for Resilient Design
 Zihan Xu, Ketul Sutaria, Chengen Yang, Chaitali Chakrabarti, Yu Cao
Arizona State University (US)
T_9 Modeling and parameter extraction of zero-VT MOSFETs for ultra-low-voltage operation
 Carlos Galup-Montoro, Marcio C. Schneider and Marcio B. Machado
Federal University of S Catarina (BR)
T_10
 Charge trapping phenomena in MOSFETS: From Noise to Bias Temperature Instability
 Gilson Wirth
UFRGS (BR)
T_11 Consistent parameter extraction using different MOSFET models
 Luiz Alberto Pasini Melek, Rodrigo Luiz de Oliveira Pinto, Manoel Alvares, Oscar Gouveia Filho, Djones Lettnin, Márcio Cherem Schneider, and Carlos Galup-Montoro
Federal University of S. Catarina (BR)

Coffee Break
Panel
 Status and Future of Verilog-A Compact Modeling Standardization
Moderator: Larry Nagel
CMC Standardization Perspective
Keith R. Green; TI, CMC  General Chair
Passive Components and Interconnect Standardization for VLSI Design
Narain D. Arora;  Silterra
Academic Perspective
 Carlos Galup-Montoro, FUSC
Gilson Wirth, UFRGS
17:00
 End of the MOS-AK Workshop

Committee:
Extended MOS-AK/GSA Committee
<
No.#17001
update: Dec. 2012 (rev. f)
Contents subject to change ©1999-2012 All rights reserved. WG
 Graphics © 2012 Oliver