Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
10th International MOS-AK Workshop
(co-located with the CMC Meeting and IEDM Conference)
Silicon Valley, December 6, 2017
Calendar
Open Directory
Books
Mission
Committee
MOS-AK: Enabling Compact Modeling R&D Exchange
Sponsor and Technical MOS-AK Program Promoters
Cadence
lead sponsor
IEEE EDS SCV  SF
EDS SCV-SF
NEEDS
powered by nanoHUB.org
Eurotraining
IJHSES
Publishing Partner
MOS-AK Workshop Program
Important Dates:
  • Call for Papers - Sept. 2017
  • 2nd Announcement - Oct. 2017
  • Final Workshop Program - Nov. 2017
  • MOS-AK Workshop - Dec.6, 2017
Venue:
Cadence Design Systems
2655 Seely Ave
San Jose, CA 95134
Building 5 (map)

Online
 registration 
Agenda 
Display Format: Citation Citation & Abstract
9:00-12:30
MOS-AK Morning Session
T_0  Welcome and MOS-AK Workshop Opening
Hany Elhak and Wladek Grabinski*
Cadence (US) and *MOS-AK (EU)
T_1  Verilog-A debug tool: AHDL Lint
Jushan Xie, Qingping Wu, Art Schaldenbrand, Andre Baguenier
Cadence (US)
T_2  A Complete Learning-Based Semiconductor Parametric Testing and Device Modeling Ecosystem, from Probing to Simulation
Yanfeng Li, Miao Li, Jian Yao, Riko Radojcic
Platform Design Automation, Inc (CN)
T_3  Generation of HICUM/L2 and HICUM/L0 Geometry Scalable Model Libraries
Didier Celi
STM (F)

Coffee Break
T_4  SOI technology platforms for 5G: opportunity of collaboration
Ionut Radu
SOITEC (F)
T_5  An Overview of the HiSIM SOI/SOTB Compact Models
Marek Mierzwinski*, Dondee Navarro**, and Mitiko Miura-Mattausch**
*Keysight Technologies (US), **Hiroshima University (J)
T_6  Featured Circuit Simulation Using SMARTSPICE Compact Models and Verilog-A
Andrei Pashkovich and Bogdan Tudor
SILVACO (US)
12:30-13:30
Lunch Break
13:30-17:00
MOS-AK Afternoon Sesson
T_7  Compact Model Requirements for TCAD Based DTCO
Asen Asenov
Glasgow University and Synopsis
T_8  Enablement of compact models for ultra-scaled CMOS technologies
Dmitry Yakimets, Pieter Schuddinck, Doyoung Jang, Marie Garcia Bardon, Neha Sharan, Bertrand Parvais, Praveen Raghavan, and Anda Mocuta
imec (B)
T_9  Rapid Co-optimization of Processing & Circuit Design to Overcome Variations
Gage Hills
Uni.Stanford (US)

Coffe Break
T_10  Dynamic Trap Density Modeling for Aging Simulation of MOSFETs
Dondee Navarro
Uni.Hiroshima (J)
T_11  Aging simulation with variation of several model parameters
Klaus-Willi Pieper
Infineon Technologies (D)
T_12  FOSS/H Tools for Compact Modeling
Wladek Grabinski
MOS-AK (EU)
T_13  Reliability characterization of discrete devices and modeling circuit level ageing in advanced CMOS technologies
Tanya Nigam and Andreas Kerber
GLOBALFOUNDRIES (US)
17:00
End of MOS-AK Workshop



Extended MOS-AK/GSA Committee:
Committee
  • International MOS-AK Board of R&D Advisers
    • Larry Nagel, Omega Enterprises Consulting (USA)
    • Andrei Vladimirescu, UCB (USA); ISEP (FR)
  • MOS-AK Workshop Manager
    • Wladek Grabinski, MOS-AK (EU)
  • Technical Committee
    MOS-AK/GSA North America
  • Chair: Pekka Ojala, Exar Corporation
  • Co-Chair: Geoffrey Coram, Analog Devices
  • Co-Chair: Prof. Jamal Deen, U.McMaster
  • Co-Chair: Roberto Tinti, Agilent EEsof Division
    MOS-AK/GSA South America
  • Chair: Prof. Gilson I Wirth; UFRGS; Brazil
  • Co-Chair: Prof. Carlos Galup-Montoro, UFSC; Brazil
  • Co-Chair: Sergio Bampi, UFRGS, Brazil
  • Co-Chair: Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
    MOS-AK/GSA Europe
  • Chair: Ehrenfried Seebacher, AMS, Austria
  • Co-Chair: Suba Subramaniam, XFab, XFab, Germany
  • Co-Chair: Prof. Benjamin Iniguez, URV, Spain
  • Co-Chair: Franz Sischka, SisConsult, Germany
    MOS-AK/GSA Asia/South Pacific

  • Chair: Sadayuki Yoshitomi, Toshiba (J)
  • Co-Chair: Min Zhang, XMOD Technologies, (CN)
  • Co-Chair: Xing Zhou, NTU Singapore (SG)  
  • Co-Chair: A.B. Bhattacharyya, JIIT New Delhi (IN)
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update: Oct. 2017 (rev. d)
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