Arbeitskreis
MOS-Modelle und Parameterextraktion MOS Modeling and Parameter Extraction Working Group MOS-AK/ESSDERC/ESSCIRC Workshop Friday, 19 September 2008 at Edinburgh International Conference Centre (EICC) |
Agenda: Friday, 19 September 2008 at Edinburgh International Conference Centre (EICC) | ||
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Sponsors of the MOS-AK Workshop |
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Technical Program Promoters |
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Workshop Program |
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9:00 | Workshop Opening: |
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9:00-11:30 | Morning Session: Towards
Nano Compact Modeling Chair: Joachim Burghartz, IMS-Chips |
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Compact Model Challenges of 65nm
RF-CMOS Technology Sadayuki Yoshitomi; TOSHIBA |
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Aspects of High-Frequency Modeling
of MOSFETs with EKV3 Matthias Bucher, Maria-Anna Chalkiadaki; TUC and Antonios Bazigos NTUA |
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LDMOS Model Benchmark of State of
the Art HV MOS Models Kund Molnár, Biswanath Senapati, Werner Posch and Ehrenfried Seebacher; austriamicrosystems AG |
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Compact Modeling Techniques in
Thin-Film SOI MOSFETs Benjamin Ińiguez; URV and Denis Flandre; UCL |
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High-level modelling and performance
optimisation of mixed-technology energy harvester systems
Tom J Kazmierski, University of Southampton |
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![]() | MOS-AK presentations recommended for further publication | |||||
11:30-12:00 | Poster
Session Chair: W.Grabinski, GMC |
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12:00-13:00 | Lunch: |
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13:00-16:00 | Afternoon
Tutorial Session: Compact
Modeling and Transistor Level Optimization in Analog Designs Chair: Peter Mole; Intersil |
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Charge-based Modeling of the MOS
Transistor
Christian Enz; CSEM, EPFL |
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Tradeoffs and Optimization in Analog
CMOS Design David M. Binkley; The University of North Carolina at Charlotte |
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16:00 | End of the MOS-AK Workshop |
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